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fit in 80 cols
llvm-svn: 74270
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@ -30,10 +30,9 @@ using namespace llvm;
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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bool IsClone, bool IsCloned,
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unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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void ScheduleDAGSDNodes::
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EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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@ -335,7 +334,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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DenseMap<SDValue, unsigned> &VRBaseMap){
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unsigned VRBase = 0;
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unsigned Opc = Node->getMachineOpcode();
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