From 1900a7e6efe4c5275e6859f2ca6c9ea0e7fc3cf2 Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard@linaro.org>
Date: Fri, 19 Jul 2019 09:59:26 +0000
Subject: [PATCH] [IPRA] Don't rely on non-exact function definitions

If a function definition is not exact, then the linker could select a
differently-compiled version of it, which could use different registers.

https://reviews.llvm.org/D64909

llvm-svn: 366557
---
 lib/CodeGen/RegUsageInfoPropagate.cpp     |  6 +++-
 test/CodeGen/ARM/ipra-exact-definition.ll | 44 +++++++++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/ARM/ipra-exact-definition.ll

diff --git a/lib/CodeGen/RegUsageInfoPropagate.cpp b/lib/CodeGen/RegUsageInfoPropagate.cpp
index fc4be82d215..0205e619374 100644
--- a/lib/CodeGen/RegUsageInfoPropagate.cpp
+++ b/lib/CodeGen/RegUsageInfoPropagate.cpp
@@ -130,7 +130,11 @@ bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
       };
 
       if (const Function *F = findCalledFunction(M, MI)) {
-        UpdateRegMask(*F);
+        if (F->isDefinitionExact()) {
+          UpdateRegMask(*F);
+        } else {
+          LLVM_DEBUG(dbgs() << "Function definition is not exact\n");
+        }
       } else {
         LLVM_DEBUG(dbgs() << "Failed to find call target function\n");
       }
diff --git a/test/CodeGen/ARM/ipra-exact-definition.ll b/test/CodeGen/ARM/ipra-exact-definition.ll
new file mode 100644
index 00000000000..2f3b3c7b39a
--- /dev/null
+++ b/test/CodeGen/ARM/ipra-exact-definition.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
+
+; A linkone_odr function (the same applies to available_externally, linkonce,
+; weak, common, extern_weak and weak_odr) could be replaced with a
+; differently-compiled version of the same source at link time, which might use
+; different registers, so we can't do IPRA on it.
+define linkonce_odr void @leaf_linkonce_odr() {
+entry:
+  ret void
+}
+define void @test_linkonce_odr() {
+; CHECK-LABEL: test_linkonce_odr:
+entry:
+; CHECK: ASM1: r3
+; CHECK: mov   [[TEMP:r[0-9]+]], r3
+; CHECK: bl    leaf_linkonce_odr
+; CHECK: mov   r3, [[TEMP]]
+; CHECK: ASM2: r3
+  %0 = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
+  tail call void @leaf_linkonce_odr()
+  %1 = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %0)
+  ret void
+}
+
+; This function has external linkage (the same applies to private, internal and
+; appending), so the version we see here is guaranteed to be the version
+; selected by the linker, so we can do IPRA.
+define external void @leaf_external() {
+entry:
+  ret void
+}
+define void @test_external() {
+; CHECK-LABEL: test_external:
+entry:
+; CHECK: ASM1: r3
+; CHECK-NOT:   r3
+; CHECK: bl    leaf_external
+; CHECK-NOT:   r3
+; CHECK: ASM2: r3
+  %0 = tail call i32 asm sideeffect "// ASM1: $0", "={r3},0"(i32 undef)
+  tail call void @leaf_external()
+  %1 = tail call i32 asm sideeffect "// ASM2: $0", "={r3},0"(i32 %0)
+  ret void
+}