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[X86] Regenerate cmpxchg tests
Add 64-bit cmpxchg8b tests llvm-svn: 326380
This commit is contained in:
Simon Pilgrim
parent
9b1a456f2b
commit
1906512dc8
@ -1,11 +1,20 @@
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; RUN: llc -mcpu=core-avx2 -mtriple=x86_64 -o - %s | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
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define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: try_cmpxchg:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmp
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; CHECK: sete %al
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; CHECK: retq
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rcx, %r9
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: movq %r9, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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ret i1 %success
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@ -13,10 +22,24 @@ define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
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define void @cmpxchg_flow(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_flow:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmp
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; CHECK-NOT: set
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; CHECK: {{jne|jeq}}
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rcx, %r9
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: movq %r9, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne .LBB1_2
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; CHECK-NEXT: # %bb.1: # %true
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; CHECK-NEXT: callq foo
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_2: # %false
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; CHECK-NEXT: callq bar
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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br i1 %success, label %true, label %false
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@ -33,9 +56,21 @@ false:
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; Can't use the flags here because cmpxchg16b only sets ZF.
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define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_arithcmp:
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; CHECK: cmpxchg16b
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; CHECK: cmpq
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; CHECK: retq
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rcx, %r9
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; CHECK-NEXT: movq %rdx, %r10
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: movq %r9, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: cmpq %rsi, %rax
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; CHECK-NEXT: sbbq %r10, %rdx
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; CHECK-NEXT: setge %al
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%oldval = extractvalue { i128, i1 } %pair, 0
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%success = icmp sge i128 %oldval, %desired
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@ -44,10 +79,21 @@ define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
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define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
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; CHECK-LABEL: cmpxchg_zext:
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; CHECK: xorl
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmpq
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; CHECK: sete
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rcx, %r9
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; CHECK-NEXT: xorl %r10d, %r10d
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: movq %r8, %rcx
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; CHECK-NEXT: movq %r9, %rbx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: sete %r10b
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movq %r10, %rax
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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%pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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%success = extractvalue { i128, i1 } %pair, 1
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%mask = zext i1 %success to i128
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@ -57,10 +103,32 @@ define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
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define i128 @cmpxchg_use_eflags_and_val(i128* %addr, i128 %offset) {
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; CHECK-LABEL: cmpxchg_use_eflags_and_val:
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; CHECK: cmpxchg16b
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; CHECK-NOT: cmpq
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; CHECK: jne
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdx, %r8
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: xorl %ebx, %ebx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB4_1: # %loop
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movq %rdx, %r9
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; CHECK-NEXT: movq %rax, %r10
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; CHECK-NEXT: movq %rax, %rbx
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; CHECK-NEXT: addq %rsi, %rbx
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: adcq %r8, %rcx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: jne .LBB4_1
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; CHECK-NEXT: # %bb.2: # %done
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; CHECK-NEXT: movq %r10, %rax
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; CHECK-NEXT: movq %r9, %rdx
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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%init = load atomic i128, i128* %addr seq_cst, align 16
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br label %loop
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@ -1,10 +1,19 @@
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
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; Basic 128-bit cmpxchg
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define void @t1(i128* nocapture %p) nounwind ssp {
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; CHECK-LABEL: t1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: movl $1, %ebx
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; CHECK-NEXT: lock cmpxchg16b (%rdi)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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; CHECK: movl $1, %ebx
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; CHECK: lock cmpxchg16b
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%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
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ret void
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}
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31
test/CodeGen/X86/cmpxchg8b.ll
Normal file
31
test/CodeGen/X86/cmpxchg8b.ll
Normal file
@ -0,0 +1,31 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
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; Basic 64-bit cmpxchg
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define void @t1(i64* nocapture %p) nounwind ssp {
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; X86-LABEL: t1:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: movl $1, %ebx
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; X86-NEXT: lock cmpxchg8b (%esi)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl
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;
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; X64-LABEL: t1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl $1, %ecx
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: lock cmpxchgq %rcx, (%rdi)
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; X64-NEXT: retq
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entry:
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%r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
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ret void
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}
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