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Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
This commit is contained in:
Duncan Sands
parent
3b9228c5ce
commit
190d6bc636
@ -119,7 +119,7 @@ public:
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/// getSetCCResultType - Return the ValueType of the result of setcc
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/// operations.
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virtual MVT getSetCCResultType(const SDValue &) const;
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virtual MVT getSetCCResultType(MVT VT) const;
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/// getBooleanContents - For targets without i1 registers, this gives the
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/// nature of the high-bits of boolean values held in types wider than i1.
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@ -2799,7 +2799,8 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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return N2;
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC, false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
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@ -4242,7 +4243,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
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SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
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// Use SimplifySetCC to simplify SETCC's.
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SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS),
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SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
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CondLHS, CondRHS, CC->get(), false);
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if (Simp.getNode()) AddToWorkList(Simp.getNode());
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@ -5437,7 +5438,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC, false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
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@ -5517,7 +5519,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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SDValue Temp, SCC;
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// cast from setcc result type to select result type
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if (LegalTypes) {
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SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
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SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()),
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N0, N1, CC);
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if (N2.getValueType().bitsLT(SCC.getValueType()))
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Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
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else
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@ -5543,8 +5546,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
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MVT XType = N0.getValueType();
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if (!LegalOperations ||
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TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
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SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
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TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
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SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC);
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if (Res.getValueType() != VT)
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Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
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return Res;
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@ -2092,7 +2092,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Tmp3 = Node->getOperand(3); // RHS
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Tmp4 = Node->getOperand(1); // CC
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LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
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LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3,Tmp4);
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LastCALLSEQ_END = DAG.getEntryNode();
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// If we didn't get both a LHS and RHS back from LegalizeSetCC,
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@ -2994,7 +2994,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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Tmp4 = LegalizeOp(Node->getOperand(3)); // False
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SDValue CC = Node->getOperand(4);
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LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
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LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC);
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// If we didn't get both a LHS and RHS back from LegalizeSetCC,
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// the LHS is a legal SETCC itself. In this case, we need to compare
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@ -3109,7 +3109,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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for (unsigned i = 0; i < NumElems; ++i) {
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SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
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Tmp1, DAG.getIntPtrConstant(i));
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Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
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Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1,
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DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
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Tmp2, DAG.getIntPtrConstant(i)),
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CC);
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@ -3371,7 +3371,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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MVT IVT =
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Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
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SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
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SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
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SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT),
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SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
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// Get the absolute value of the result.
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SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
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@ -3736,7 +3736,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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case ISD::CTTZ:
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//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
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DAG.getConstant(NVT.getSizeInBits(), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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@ -3798,8 +3798,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
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MVT VT = Node->getValueType(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
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ISD::SETUGT);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
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Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
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break;
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@ -4069,8 +4069,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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APInt x = APInt::getSignBit(NVT.getSizeInBits());
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(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
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Tmp2 = DAG.getConstantFP(apf, VT);
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Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
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Node->getOperand(0), Tmp2, ISD::SETLT);
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Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(VT), Node->getOperand(0),
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Tmp2, ISD::SETLT);
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True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
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False = DAG.getNode(ISD::FP_TO_SINT, NVT,
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DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
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@ -4484,15 +4484,15 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
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break;
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case ISD::SETCC:
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assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
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case ISD::SETCC: {
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MVT VT0 = Node->getOperand(0).getValueType();
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assert(isTypeLegal(TLI.getSetCCResultType(VT0))
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&& "SetCC type is not legal??");
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Result = DAG.getNode(ISD::SETCC,
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TLI.getSetCCResultType(Node->getOperand(0)),
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Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0),
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Node->getOperand(0), Node->getOperand(1),
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Node->getOperand(2));
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break;
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}
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case ISD::TRUNCATE:
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Legal:
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@ -4898,7 +4898,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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break;
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case ISD::CTTZ:
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// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
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DAG.getConstant(NVT.getSizeInBits(), NVT),
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ISD::SETEQ);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
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@ -5167,12 +5167,14 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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Tmp2 = DAG.getConstant(0, MVT::i32);
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CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
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if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
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Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
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CC);
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Tmp1 = DAG.getNode(ISD::SETCC,
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TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, CC);
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LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
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false /*sign irrelevant*/, Dummy);
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
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DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
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Tmp2 = DAG.getNode(ISD::SETCC,
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TLI.getSetCCResultType(LHS.getValueType()), LHS,
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Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
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Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp2 = SDValue();
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}
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@ -5192,13 +5194,15 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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// BNE crN, L:
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// FCMPU crN, lo1, lo2
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// The following can be improved, but not that much.
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETOEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETOEQ);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, CCCode);
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Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETUNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETUNE);
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Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
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Tmp2 = SDValue();
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@ -5256,15 +5260,17 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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// NOTE: on targets without efficient SELECT of bools, we can always use
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// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
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TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
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LowCC, false, DagCombineInfo);
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Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC, false, DagCombineInfo);
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if (!Tmp1.getNode())
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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CCCode, false, DagCombineInfo);
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Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, LowCC);
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Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, CCCode, false, DagCombineInfo);
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if (!Tmp2.getNode())
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
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RHSHi,CC);
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Tmp2 = DAG.getNode(ISD::SETCC,
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TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi,CC);
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ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
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ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
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@ -5281,11 +5287,12 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
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Tmp1 = Tmp2;
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Tmp2 = SDValue();
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} else {
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Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETEQ, false, DagCombineInfo);
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Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ, false,
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DagCombineInfo);
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if (!Result.getNode())
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Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
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ISD::SETEQ);
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Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETEQ);
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Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
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Result, Tmp1, Tmp2));
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Tmp1 = Result;
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@ -5909,9 +5916,9 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
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// signed, then adjust the result if the sign bit is set.
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SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
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SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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DAG.getConstant(0, Hi.getValueType()),
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ISD::SETLT);
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SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
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Hi, DAG.getConstant(0, Hi.getValueType()),
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ISD::SETLT);
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SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
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SignSet, Four, Zero);
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@ -6050,9 +6057,9 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
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SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
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SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
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DAG.getConstant(0, Op0.getValueType()),
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ISD::SETLT);
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SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0.getValueType()),
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Op0, DAG.getConstant(0, Op0.getValueType()),
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ISD::SETLT);
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SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
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SignSet, Four, Zero);
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@ -6458,8 +6465,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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ExpandOp(Node->getOperand(0), Lo, Hi);
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SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
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SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
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SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
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ISD::SETNE);
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SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC,
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ISD::SETNE);
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SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
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LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
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@ -6473,8 +6480,8 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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ExpandOp(Node->getOperand(0), Lo, Hi);
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SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
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SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
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SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
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ISD::SETNE);
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SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC,
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ISD::SETNE);
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SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
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HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
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@ -6950,12 +6957,12 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
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Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
|
||||
SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
|
||||
SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
|
||||
Lo, LoOps[0], ISD::SETULT);
|
||||
SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
|
||||
DAG.getConstant(1, NVT),
|
||||
DAG.getConstant(0, NVT));
|
||||
SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
|
||||
SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT),
|
||||
Lo, LoOps[1], ISD::SETULT);
|
||||
SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
|
||||
DAG.getConstant(1, NVT),
|
||||
@ -7875,8 +7882,8 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
|
||||
case ISD::VSETCC: {
|
||||
SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
|
||||
SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
|
||||
Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
|
||||
Op.getOperand(2));
|
||||
Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()),
|
||||
Op0, Op1, Op.getOperand(2));
|
||||
Result = DAG.getNode(ISD::SELECT, NewVT, Result,
|
||||
DAG.getConstant(-1ULL, NewVT),
|
||||
DAG.getConstant(0ULL, NewVT));
|
||||
|
||||
@ -594,10 +594,10 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
|
||||
NewRHS = DAG.getConstant(0, RetVT);
|
||||
CCCode = TLI.getCmpLibcallCC(LC1);
|
||||
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
|
||||
SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS),
|
||||
SDValue Tmp = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT),
|
||||
NewLHS, NewRHS, DAG.getCondCode(CCCode));
|
||||
NewLHS = MakeLibCall(LC2, RetVT, Ops, 2, false/*sign irrelevant*/);
|
||||
NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(NewLHS), NewLHS,
|
||||
NewLHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(RetVT), NewLHS,
|
||||
NewRHS, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
|
||||
NewLHS = DAG.getNode(ISD::OR, Tmp.getValueType(), Tmp, NewLHS);
|
||||
NewRHS = SDValue();
|
||||
@ -1216,11 +1216,15 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
|
||||
// FCMPU crN, lo1, lo2
|
||||
// The following can be improved, but not that much.
|
||||
SDValue Tmp1, Tmp2, Tmp3;
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETOEQ);
|
||||
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETOEQ);
|
||||
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
|
||||
LHSLo, RHSLo, CCCode);
|
||||
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETUNE);
|
||||
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETUNE);
|
||||
Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, CCCode);
|
||||
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
|
||||
NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
|
||||
NewRHS = SDValue(); // LHS is the result, not a compare.
|
||||
|
||||
@ -464,7 +464,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
|
||||
}
|
||||
|
||||
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
|
||||
MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
|
||||
MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
|
||||
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
|
||||
|
||||
// Get the SETCC result using the canonical SETCC type.
|
||||
@ -728,25 +728,42 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
|
||||
assert(OpNo == 1 && "only know how to promote condition");
|
||||
SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
|
||||
|
||||
// Make sure the extra bits coming from type promotion conform to
|
||||
// getBooleanContents.
|
||||
// Promote all the way up to SVT, the canonical SetCC type.
|
||||
MVT SVT = TLI.getSetCCResultType(MVT::Other);
|
||||
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
|
||||
assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
|
||||
|
||||
// Make sure the extra bits conform to getBooleanContents. There are
|
||||
// two sets of extra bits: those in Cond, which come from type promotion,
|
||||
// and those we need to add to have the final type be SVT (for most targets
|
||||
// this last set of bits is empty).
|
||||
unsigned CondBits = Cond.getValueSizeInBits();
|
||||
ISD::NodeType ExtendCode;
|
||||
switch (TLI.getBooleanContents()) {
|
||||
default:
|
||||
assert(false && "Unknown BooleanContent!");
|
||||
case TargetLowering::UndefinedBooleanContent:
|
||||
// The promoted value, which may contain rubbish in the upper bits, is fine.
|
||||
// Extend to SVT by adding rubbish.
|
||||
ExtendCode = ISD::ANY_EXTEND;
|
||||
break;
|
||||
case TargetLowering::ZeroOrOneBooleanContent:
|
||||
ExtendCode = ISD::ZERO_EXTEND;
|
||||
if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
|
||||
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
|
||||
// All extra bits need to be cleared. Do this by zero extending the
|
||||
// original condition value all the way to SVT.
|
||||
Cond = N->getOperand(1);
|
||||
break;
|
||||
case TargetLowering::ZeroOrNegativeOneBooleanContent:
|
||||
if (DAG.ComputeNumSignBits(Cond) != CondBits)
|
||||
Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
|
||||
DAG.getValueType(MVT::i1));
|
||||
case TargetLowering::ZeroOrNegativeOneBooleanContent: {
|
||||
ExtendCode = ISD::SIGN_EXTEND;
|
||||
unsigned SignBits = DAG.ComputeNumSignBits(Cond);
|
||||
if (SignBits != CondBits)
|
||||
// All extra bits need to be sign extended. Do this by sign extending the
|
||||
// original condition value all the way to SVT.
|
||||
Cond = N->getOperand(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Cond = DAG.getNode(ExtendCode, SVT, Cond);
|
||||
|
||||
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
|
||||
return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
|
||||
@ -851,13 +868,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
|
||||
SDValue Cond = GetPromotedInteger(N->getOperand(0));
|
||||
|
||||
// Promote all the way up to SVT, the canonical SetCC type.
|
||||
// FIXME: Not clear what value to pass to getSetCCResultType.
|
||||
// [This only matters for CellSPU since all other targets
|
||||
// ignore the argument.] We used to pass Cond, resulting in
|
||||
// SVT = MVT::i8, but CellSPU has no select patterns for i8,
|
||||
// causing an abort later. Passing the result type works
|
||||
// around the problem.
|
||||
MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
|
||||
MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
|
||||
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
|
||||
assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
|
||||
|
||||
@ -1244,12 +1255,12 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
||||
if (N->getOpcode() == ISD::ADD) {
|
||||
Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
|
||||
Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
|
||||
SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
|
||||
SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[0],
|
||||
ISD::SETULT);
|
||||
SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
|
||||
DAG.getConstant(1, NVT),
|
||||
DAG.getConstant(0, NVT));
|
||||
SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
|
||||
SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[1],
|
||||
ISD::SETULT);
|
||||
SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
|
||||
DAG.getConstant(1, NVT), Carry1);
|
||||
@ -1257,8 +1268,9 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
||||
} else {
|
||||
Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
|
||||
Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
|
||||
SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]),
|
||||
LoOps[0], LoOps[1], ISD::SETULT);
|
||||
SDValue Cmp =
|
||||
DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()),
|
||||
LoOps[0], LoOps[1], ISD::SETULT);
|
||||
SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
|
||||
DAG.getConstant(1, NVT),
|
||||
DAG.getConstant(0, NVT));
|
||||
@ -1391,7 +1403,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
|
||||
GetExpandedInteger(N->getOperand(0), Lo, Hi);
|
||||
MVT NVT = Lo.getValueType();
|
||||
|
||||
SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
|
||||
SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Hi,
|
||||
DAG.getConstant(0, NVT), ISD::SETNE);
|
||||
|
||||
SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
|
||||
@ -1419,7 +1431,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
|
||||
GetExpandedInteger(N->getOperand(0), Lo, Hi);
|
||||
MVT NVT = Lo.getValueType();
|
||||
|
||||
SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
|
||||
SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo,
|
||||
DAG.getConstant(0, NVT), ISD::SETNE);
|
||||
|
||||
SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
|
||||
@ -2007,15 +2019,16 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
|
||||
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
|
||||
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
|
||||
SDValue Tmp1, Tmp2;
|
||||
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
|
||||
false, DagCombineInfo);
|
||||
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
|
||||
LHSLo, RHSLo, LowCC, false, DagCombineInfo);
|
||||
if (!Tmp1.getNode())
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
|
||||
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
CCCode, false, DagCombineInfo);
|
||||
Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
|
||||
LHSLo, RHSLo, LowCC);
|
||||
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, CCCode, false, DagCombineInfo);
|
||||
if (!Tmp2.getNode())
|
||||
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
DAG.getCondCode(CCCode));
|
||||
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, DAG.getCondCode(CCCode));
|
||||
|
||||
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
|
||||
ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
|
||||
@ -2034,11 +2047,11 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
|
||||
return;
|
||||
}
|
||||
|
||||
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
ISD::SETEQ, false, DagCombineInfo);
|
||||
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo);
|
||||
if (!NewLHS.getNode())
|
||||
NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
|
||||
ISD::SETEQ);
|
||||
NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETEQ);
|
||||
NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
|
||||
NewLHS, Tmp1, Tmp2);
|
||||
NewRHS = SDValue();
|
||||
@ -2223,8 +2236,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
|
||||
// Check whether the sign bit is set.
|
||||
SDValue Lo, Hi;
|
||||
GetExpandedInteger(Op, Lo, Hi);
|
||||
SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
|
||||
DAG.getConstant(0, Hi.getValueType()),
|
||||
SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
|
||||
Hi, DAG.getConstant(0, Hi.getValueType()),
|
||||
ISD::SETLT);
|
||||
|
||||
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
|
||||
|
||||
@ -216,7 +216,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
|
||||
SDValue LHS = GetScalarizedVector(N->getOperand(0));
|
||||
SDValue RHS = GetScalarizedVector(N->getOperand(1));
|
||||
MVT NVT = N->getValueType(0).getVectorElementType();
|
||||
MVT SVT = TLI.getSetCCResultType(LHS);
|
||||
MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
|
||||
|
||||
// Turn it into a scalar SETCC.
|
||||
SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
|
||||
|
||||
@ -1369,7 +1369,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
|
||||
// Emit the range check for the jump table, and branch to the default block
|
||||
// for the switch statement if the value being switched on exceeds the largest
|
||||
// case in the switch.
|
||||
SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
||||
SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
|
||||
DAG.getConstant(JTH.Last-JTH.First,VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
@ -1402,7 +1402,7 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
|
||||
DAG.getConstant(B.First, VT));
|
||||
|
||||
// Check range
|
||||
SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB,
|
||||
SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
|
||||
DAG.getConstant(B.Range, VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
@ -1455,8 +1455,8 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
|
||||
|
||||
SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
|
||||
DAG.getConstant(B.Mask, TLI.getPointerTy()));
|
||||
SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp,
|
||||
DAG.getConstant(0, TLI.getPointerTy()),
|
||||
SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
|
||||
AndOp, DAG.getConstant(0, TLI.getPointerTy()),
|
||||
ISD::SETNE);
|
||||
|
||||
CurMBB->addSuccessor(B.TargetBB);
|
||||
|
||||
@ -607,7 +607,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
|
||||
|
||||
MVT TargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT TargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return getValueType(TD->getIntPtrType());
|
||||
}
|
||||
|
||||
|
||||
@ -159,7 +159,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
|
||||
computeRegisterProperties();
|
||||
}
|
||||
|
||||
MVT AlphaTargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT AlphaTargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return MVT::i64;
|
||||
}
|
||||
|
||||
|
||||
@ -67,7 +67,7 @@ namespace llvm {
|
||||
explicit AlphaTargetLowering(TargetMachine &TM);
|
||||
|
||||
/// getSetCCResultType - Get the SETCC result ValueType
|
||||
virtual MVT getSetCCResultType(const SDValue &) const;
|
||||
virtual MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
///
|
||||
|
||||
@ -433,8 +433,7 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
|
||||
// Return the Cell SPU's SETCC result type
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
MVT SPUTargetLowering::getSetCCResultType(const SDValue &Op) const {
|
||||
MVT VT = Op.getValueType();
|
||||
MVT SPUTargetLowering::getSetCCResultType(MVT VT) const {
|
||||
// i16 and i32 are valid SETCC result types
|
||||
return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ? VT : MVT::i32);
|
||||
}
|
||||
@ -2510,7 +2509,8 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
|
||||
// legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
|
||||
// with another "cannot select select_cc" assert:
|
||||
|
||||
SDValue compare = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op),
|
||||
SDValue compare = DAG.getNode(ISD::SETCC,
|
||||
TLI.getSetCCResultType(Op.getValueType()),
|
||||
lhs, rhs, condition);
|
||||
return DAG.getNode(SPUISD::SELB, VT, falseval, trueval, compare);
|
||||
}
|
||||
|
||||
@ -95,7 +95,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ValueType for ISD::SETCC
|
||||
virtual MVT getSetCCResultType(const SDValue &) const;
|
||||
virtual MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
//! Custom lowering hooks
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
|
||||
|
||||
@ -140,7 +140,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
}
|
||||
|
||||
MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return MVT::i1;
|
||||
}
|
||||
|
||||
|
||||
@ -49,7 +49,7 @@ namespace llvm {
|
||||
const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType: return ISD::SETCC's result type.
|
||||
virtual MVT getSetCCResultType(const SDValue &) const;
|
||||
virtual MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
/// LowerArguments - This hook must be implemented to indicate how we should
|
||||
/// lower the arguments for the specified function, into the specified DAG.
|
||||
|
||||
@ -152,7 +152,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
|
||||
}
|
||||
|
||||
|
||||
MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT MipsTargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
|
||||
|
||||
@ -79,7 +79,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - get the ISD::SETCC result ValueType
|
||||
MVT getSetCCResultType(const SDValue &) const;
|
||||
MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
private:
|
||||
// Subtarget Info
|
||||
|
||||
@ -432,7 +432,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
|
||||
|
||||
MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
|
||||
|
||||
@ -231,7 +231,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual MVT getSetCCResultType(const SDValue &) const;
|
||||
virtual MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
||||
/// offset pointer and addressing mode by reference if the node's address
|
||||
|
||||
@ -819,7 +819,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
}
|
||||
|
||||
|
||||
MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
|
||||
MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
|
||||
return MVT::i8;
|
||||
}
|
||||
|
||||
|
||||
@ -400,7 +400,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual MVT getSetCCResultType(const SDValue &) const;
|
||||
virtual MVT getSetCCResultType(MVT VT) const;
|
||||
|
||||
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
||||
/// in Mask are known to be either zero or one and return them in the
|
||||
|
||||
31
test/CodeGen/CellSPU/2009-01-01-BrCond.ll
Normal file
31
test/CodeGen/CellSPU/2009-01-01-BrCond.ll
Normal file
@ -0,0 +1,31 @@
|
||||
; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brnz
|
||||
; PR3274
|
||||
|
||||
target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
|
||||
target triple = "spu"
|
||||
%struct.anon = type { i64 }
|
||||
%struct.fp_number_type = type { i32, i32, i32, [4 x i8], %struct.anon }
|
||||
|
||||
define double @__floatunsidf(i32 %arg_a) nounwind {
|
||||
entry:
|
||||
%in = alloca %struct.fp_number_type, align 8 ; <%struct.fp_number_type*> [#uses=5]
|
||||
%0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1 ; <i32*> [#uses=1]
|
||||
store i32 0, i32* %0, align 4
|
||||
%1 = icmp eq i32 %arg_a, 0 ; <i1> [#uses=1]
|
||||
%2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0 ; <i32*> [#uses=2]
|
||||
br i1 %1, label %bb, label %bb1
|
||||
|
||||
bb: ; preds = %entry
|
||||
store i32 2, i32* %2, align 8
|
||||
br label %bb7
|
||||
|
||||
bb1: ; preds = %entry
|
||||
ret double 0.0
|
||||
|
||||
bb7: ; preds = %bb5, %bb1, %bb
|
||||
ret double 1.0
|
||||
}
|
||||
|
||||
declare i32 @llvm.ctlz.i32(i32) nounwind readnone
|
||||
|
||||
declare double @__pack_d(%struct.fp_number_type*)
|
||||
Loading…
Reference in New Issue
Block a user