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[GlobalISel][X86] Use correct physical register in mir tests.NFC.

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llvm-svn: 313479
This commit is contained in:
Igor Breger 2017-09-17 08:30:42 +00:00
parent f5aca70376
commit 1945fdd96b
19 changed files with 122 additions and 124 deletions
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16
test/CodeGen/X86/GlobalISel/legalize-cmp.mir
View File

@ -43,8 +43,8 @@ registers:
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK-NEXT: %1(s8) = COPY %esi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s8) = COPY %sil
# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s8), %1
# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
# CHECK-NEXT: %eax = COPY %3(s32)
@ -53,8 +53,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s1) = G_ICMP intpred(ult), %0(s8), %1
%3(s32) = G_ZEXT %2(s1)
%eax = COPY %3(s32)
@ -72,8 +72,8 @@ registers:
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
# CHECK: %0(s16) = COPY %edi
# CHECK-NEXT: %1(s16) = COPY %esi
# CHECK: %0(s16) = COPY %di
# CHECK-NEXT: %1(s16) = COPY %si
# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s16), %1
# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
# CHECK-NEXT: %eax = COPY %3(s32)
@ -82,8 +82,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s1) = G_ICMP intpred(ult), %0(s16), %1
%3(s32) = G_ZEXT %2(s1)
%eax = COPY %3(s32)

36
test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
View File

@ -71,7 +71,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
# CHECK-NEXT: %2(s64) = G_SEXT %1(s1)
# CHECK-NEXT: %rax = COPY %2(s64)
@ -80,7 +80,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_SEXT %1(s1)
%rax = COPY %2(s64)
@ -96,7 +96,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s64) = G_SEXT %0(s8)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -104,7 +104,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s64) = G_SEXT %0(s8)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -119,7 +119,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s16) = COPY %edi
# CHECK: %0(s16) = COPY %di
# CHECK-NEXT: %1(s64) = G_SEXT %0(s16)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -127,7 +127,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s64) = G_SEXT %0(s16)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -166,7 +166,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
# CHECK-NEXT: %2(s64) = G_ZEXT %1(s1)
# CHECK-NEXT: %rax = COPY %2(s64)
@ -175,7 +175,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ZEXT %1(s1)
%rax = COPY %2(s64)
@ -191,7 +191,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s64) = G_ZEXT %0(s8)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -199,7 +199,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s64) = G_ZEXT %0(s8)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -214,7 +214,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s16) = COPY %edi
# CHECK: %0(s16) = COPY %di
# CHECK-NEXT: %1(s64) = G_ZEXT %0(s16)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -222,7 +222,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s64) = G_ZEXT %0(s16)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -261,7 +261,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s1) = G_TRUNC %0(s8)
# CHECK-NEXT: %2(s64) = G_ANYEXT %1(s1)
# CHECK-NEXT: %rax = COPY %2(s64)
@ -270,7 +270,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ANYEXT %1(s1)
%rax = COPY %2(s64)
@ -286,7 +286,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s64) = G_ANYEXT %0(s8)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -294,7 +294,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s64) = G_ANYEXT %0(s8)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -309,7 +309,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: %0(s16) = COPY %edi
# CHECK: %0(s16) = COPY %di
# CHECK-NEXT: %1(s64) = G_ANYEXT %0(s16)
# CHECK-NEXT: %rax = COPY %1(s64)
# CHECK-NEXT: RET 0, implicit %rax
@ -317,7 +317,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s64) = G_ANYEXT %0(s16)
%rax = COPY %1(s64)
RET 0, implicit %rax

48
test/CodeGen/X86/GlobalISel/legalize-ext.mir
View File

@ -145,7 +145,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s1) = G_TRUNC %0(s8)
# ALL-NEXT: %2(s32) = G_ZEXT %1(s1)
# ALL-NEXT: %eax = COPY %2(s32)
@ -154,7 +154,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ZEXT %1(s1)
%eax = COPY %2(s32)
@ -170,7 +170,7 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s16) = G_ZEXT %0(s8)
# ALL-NEXT: %ax = COPY %1(s16)
# ALL-NEXT: RET 0, implicit %ax
@ -178,7 +178,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s16) = G_ZEXT %0(s8)
%ax = COPY %1(s16)
RET 0, implicit %ax
@ -193,7 +193,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s32) = G_ZEXT %0(s8)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -201,7 +201,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s32) = G_ZEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -216,7 +216,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s16) = COPY %edi
# ALL: %0(s16) = COPY %di
# ALL-NEXT: %1(s32) = G_ZEXT %0(s16)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -224,7 +224,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s32) = G_ZEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -286,7 +286,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s1) = G_TRUNC %0(s8)
# ALL-NEXT: %2(s32) = G_SEXT %1(s1)
# ALL-NEXT: %eax = COPY %2(s32)
@ -295,7 +295,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_SEXT %1(s1)
%eax = COPY %2(s32)
@ -311,7 +311,7 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s16) = G_SEXT %0(s8)
# ALL-NEXT: %ax = COPY %1(s16)
# ALL-NEXT: RET 0, implicit %ax
@ -319,7 +319,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s16) = G_SEXT %0(s8)
%ax = COPY %1(s16)
RET 0, implicit %ax
@ -334,7 +334,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s32) = G_SEXT %0(s8)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -342,7 +342,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s32) = G_SEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -357,7 +357,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s16) = COPY %edi
# ALL: %0(s16) = COPY %di
# ALL-NEXT: %1(s32) = G_SEXT %0(s16)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -365,7 +365,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s32) = G_SEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -427,7 +427,7 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s1) = G_TRUNC %0(s8)
# ALL-NEXT: %2(s32) = G_ANYEXT %1(s1)
# ALL-NEXT: %eax = COPY %2(s32)
@ -436,7 +436,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ANYEXT %1(s1)
%eax = COPY %2(s32)
@ -452,7 +452,7 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s16) = G_ANYEXT %0(s8)
# ALL-NEXT: %ax = COPY %1(s16)
# ALL-NEXT: RET 0, implicit %ax
@ -460,7 +460,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s16) = G_ANYEXT %0(s8)
%ax = COPY %1(s16)
RET 0, implicit %ax
@ -475,7 +475,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s8) = COPY %edi
# ALL: %0(s8) = COPY %dil
# ALL-NEXT: %1(s32) = G_ANYEXT %0(s8)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -483,7 +483,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s32) = G_ANYEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -498,7 +498,7 @@ regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# ALL: %0(s16) = COPY %edi
# ALL: %0(s16) = COPY %di
# ALL-NEXT: %1(s32) = G_ANYEXT %0(s16)
# ALL-NEXT: %eax = COPY %1(s32)
# ALL-NEXT: RET 0, implicit %eax
@ -506,7 +506,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s32) = G_ANYEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax

8
test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
View File

@ -22,7 +22,7 @@ registers:
# ALL: %0(<16 x s32>) = COPY %zmm0
# ALL-NEXT: %1(<4 x s32>) = COPY %xmm1
# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>)
# ALL-NEXT: %zmm0 = COPY %2(<16 x s32>)
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -31,7 +31,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
@ -48,7 +48,7 @@ registers:
# ALL: %0(<16 x s32>) = COPY %zmm0
# ALL-NEXT: %1(<8 x s32>) = COPY %ymm1
# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<8 x s32>), 0
# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>)
# ALL-NEXT: %zmm0 = COPY %2(<16 x s32>)
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -57,7 +57,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...

8
test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
View File

@ -33,8 +33,8 @@ registers:
- { id: 2, class: _ }
# CHECK: body: |
# CHECK-NEXT: bb.0 (%ir-block.0):
# CHECK-NEXT: %0(s16) = COPY %edi
# CHECK-NEXT: %1(s16) = COPY %esi
# CHECK-NEXT: %0(s16) = COPY %di
# CHECK-NEXT: %1(s16) = COPY %si
# CHECK-NEXT: %2(s16) = G_MUL %0, %1
# CHECK-NEXT: %ax = COPY %2(s16)
# CHECK-NEXT: RET 0, implicit %ax
@ -42,8 +42,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_MUL %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax

8
test/CodeGen/X86/GlobalISel/legalize-phi.mir
View File

@ -210,7 +210,7 @@ constants:
# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
# ALL-NEXT: liveins: %edi, %edx, %esi
# ALL: %0(s32) = COPY %edi
# ALL-NEXT: %1(s8) = COPY %esi
# ALL-NEXT: %1(s8) = COPY %sil
# ALL-NEXT: %2(s8) = COPY %edx
# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
@ -233,7 +233,7 @@ body: |
liveins: %edi, %edx, %esi
%0(s32) = COPY %edi
%1(s8) = COPY %esi
%1(s8) = COPY %sil
%2(s8) = COPY %edx
%3(s32) = G_CONSTANT i32 0
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3
@ -277,7 +277,7 @@ constants:
# ALL-NEXT: successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
# ALL-NEXT: liveins: %edi, %edx, %esi
# ALL: %0(s32) = COPY %edi
# ALL-NEXT: %1(s16) = COPY %esi
# ALL-NEXT: %1(s16) = COPY %si
# ALL-NEXT: %2(s16) = COPY %edx
# ALL-NEXT: %3(s32) = G_CONSTANT i32 0
# ALL-NEXT: %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
@ -300,7 +300,7 @@ body: |
liveins: %edi, %edx, %esi
%0(s32) = COPY %edi
%1(s16) = COPY %esi
%1(s16) = COPY %si
%2(s16) = COPY %edx
%3(s32) = G_CONSTANT i32 0
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3

20
test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
View File

@ -262,8 +262,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s8) = G_ADD %0, %1
%al = COPY %2(s8)
RET 0, implicit %al
@ -289,8 +289,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_ADD %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax
@ -973,8 +973,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s1) = G_ICMP intpred(eq), %0(s8), %1
%al = COPY %2(s1)
RET 0, implicit %al
@ -998,8 +998,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s1) = G_ICMP intpred(eq), %0(s16), %1
%al = COPY %2(s1)
RET 0, implicit %al
@ -1213,7 +1213,7 @@ liveins:
fixedStack:
stack:
constants:
# CHECK: %0(s8) = COPY %edi
# CHECK: %0(s8) = COPY %dil
# CHECK-NEXT: %1(s8) = G_IMPLICIT_DEF
# CHECK-NEXT: %2(s8) = G_ADD %0, %1
# CHECK-NEXT: %al = COPY %2(s8)
@ -1222,7 +1222,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s8) = G_IMPLICIT_DEF
%2(s8) = G_ADD %0, %1
%al = COPY %2(s8)

8
test/CodeGen/X86/GlobalISel/select-add.mir
View File

@ -110,8 +110,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_ADD %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax
@ -139,8 +139,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s8) = G_ADD %0, %1
%al = COPY %2(s8)
RET 0, implicit %al

8
test/CodeGen/X86/GlobalISel/select-and-scalar.mir
View File

@ -49,8 +49,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s8) = G_AND %0, %1
%al = COPY %2(s8)
RET 0, implicit %al
@ -83,8 +83,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_AND %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax

8
test/CodeGen/X86/GlobalISel/select-cmp.mir
View File

@ -109,8 +109,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s1) = G_ICMP intpred(eq), %0(s8), %1
%3(s32) = G_ZEXT %2(s1)
%eax = COPY %3(s32)
@ -146,8 +146,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s1) = G_ICMP intpred(eq), %0(s16), %1
%3(s32) = G_ZEXT %2(s1)
%eax = COPY %3(s32)

6
test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
View File

@ -47,7 +47,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ZEXT %1(s1)
%rax = COPY %2(s64)
@ -74,7 +74,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s64) = G_SEXT %0(s8)
%rax = COPY %1(s64)
RET 0, implicit %rax
@ -100,7 +100,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s64) = G_SEXT %0(s16)
%rax = COPY %1(s64)
RET 0, implicit %rax

8
test/CodeGen/X86/GlobalISel/select-ext.mir
View File

@ -147,7 +147,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s32) = G_ZEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -173,7 +173,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s32) = G_ZEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -199,7 +199,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s32) = G_SEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@ -225,7 +225,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s16) = COPY %edi
%0(s16) = COPY %di
%1(s32) = G_SEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax

33
test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
View File

@ -51,7 +51,7 @@ registers:
# ALL: %0 = COPY %zmm0
# ALL-NEXT: %1 = COPY %xmm1
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 0
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -60,7 +60,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
@ -80,7 +80,7 @@ registers:
- { id: 2, class: vecr }
# ALL: %1 = COPY %xmm1
# ALL-NEXT: undef %2.sub_xmm = COPY %1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -89,7 +89,7 @@ body: |
%0(<16 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
@ -110,7 +110,7 @@ registers:
# ALL: %0 = COPY %zmm0
# ALL-NEXT: %1 = COPY %xmm1
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -119,7 +119,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
---
@ -139,7 +139,7 @@ registers:
# ALL: %0 = IMPLICIT_DEF
# ALL-NEXT: %1 = COPY %xmm1
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -148,7 +148,7 @@ body: |
%0(<16 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = COPY %xmm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
---
@ -168,7 +168,7 @@ registers:
# ALL: %0 = COPY %zmm0
# ALL-NEXT: %1 = COPY %ymm1
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 0
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -177,7 +177,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
@ -197,7 +197,7 @@ registers:
- { id: 2, class: vecr }
# ALL: %1 = COPY %ymm1
# ALL-NEXT: undef %2.sub_ymm = COPY %1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -206,7 +206,7 @@ body: |
%0(<16 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
@ -227,7 +227,7 @@ registers:
# ALL: %0 = COPY %zmm0
# ALL-NEXT: %1 = COPY %ymm1
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -236,7 +236,7 @@ body: |
%0(<16 x s32>) = COPY %zmm0
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...
---
@ -256,7 +256,7 @@ registers:
# ALL: %0 = IMPLICIT_DEF
# ALL-NEXT: %1 = COPY %ymm1
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
# ALL-NEXT: %ymm0 = COPY %2
# ALL-NEXT: %zmm0 = COPY %2
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
@ -265,7 +265,6 @@ body: |
%0(<16 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = COPY %ymm1
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
%ymm0 = COPY %2(<16 x s32>)
%zmm0 = COPY %2(<16 x s32>)
RET 0, implicit %ymm0
...

4
test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
View File

@ -41,8 +41,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_MUL %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax

8
test/CodeGen/X86/GlobalISel/select-or-scalar.mir
View File

@ -49,8 +49,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s8) = G_OR %0, %1
%al = COPY %2(s8)
RET 0, implicit %al
@ -83,8 +83,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_OR %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax

4
test/CodeGen/X86/GlobalISel/select-phi.mir
View File

@ -130,7 +130,7 @@ body: |
liveins: %edi, %edx, %esi
%0(s32) = COPY %edi
%1(s8) = COPY %esi
%1(s8) = COPY %sil
%2(s8) = COPY %edx
%3(s32) = G_CONSTANT i32 0
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3
@ -183,7 +183,7 @@ body: |
liveins: %edi, %edx, %esi
%0(s32) = COPY %edi
%1(s16) = COPY %esi
%1(s16) = COPY %si
%2(s16) = COPY %edx
%3(s32) = G_CONSTANT i32 0
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3

2
test/CodeGen/X86/GlobalISel/select-undef.mir
View File

@ -62,7 +62,7 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi
%0(s8) = COPY %edi
%0(s8) = COPY %dil
%1(s8) = G_IMPLICIT_DEF
%2(s8) = G_ADD %0, %1
%al = COPY %2(s8)

5
test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
View File

@ -60,15 +60,14 @@ registers:
# ALL: %0 = IMPLICIT_DEF
# ALL-NEXT: %1 = COPY %0.sub_ymm
# ALL-NEXT: %2 = VEXTRACTF64x4Zrr %0, 1
# ALL-NEXT: %xmm0 = COPY %1
# ALL-NEXT: %ymm0 = COPY %1
# ALL-NEXT: RET 0, implicit %ymm0
body: |
bb.1 (%ir-block.0):
%0(<16 x s32>) = IMPLICIT_DEF
%1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
%xmm0 = COPY %1(<8 x s32>)
%ymm0 = COPY %1(<8 x s32>)
RET 0, implicit %ymm0
...

8
test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
View File

@ -49,8 +49,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s8) = COPY %edi
%1(s8) = COPY %esi
%0(s8) = COPY %dil
%1(s8) = COPY %sil
%2(s8) = G_XOR %0, %1
%al = COPY %2(s8)
RET 0, implicit %al
@ -83,8 +83,8 @@ body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
%0(s16) = COPY %edi
%1(s16) = COPY %esi
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_XOR %0, %1
%ax = COPY %2(s16)
RET 0, implicit %ax