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[PowerPC] Miscellaneous fast-isel test cases.
Here are a few more tests that now pass after the recent fast-isel commits. llvm-svn: 189637
This commit is contained in:
Bill Schmidt
parent
b3f46e50b4
commit
19810417cb
48
test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
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48
test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
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@ -0,0 +1,48 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
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%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
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@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
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@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
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@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
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define i32* @t1() nounwind {
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entry:
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; ELF64: t1
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t2() nounwind {
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entry:
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; ELF64: t2
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t3() nounwind {
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entry:
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; ELF64: t3
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t4() nounwind {
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entry:
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; ELF64: t4
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
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; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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23
test/CodeGen/PowerPC/fast-isel-crash.ll
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23
test/CodeGen/PowerPC/fast-isel-crash.ll
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@ -0,0 +1,23 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
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; Ensure this doesn't crash.
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%union.anon = type { <16 x i32> }
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@__md0 = external global [137 x i8]
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define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind {
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entry:
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ret void
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}
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define internal i32 @_Z13get_global_idj(i32 %dim) nounwind ssp {
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entry:
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ret i32 undef
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}
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define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp {
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entry:
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call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef)
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ret void
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}
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10
test/CodeGen/PowerPC/fast-isel-redefinition.ll
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10
test/CodeGen/PowerPC/fast-isel-redefinition.ll
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@ -0,0 +1,10 @@
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; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
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; This isn't exactly a useful set of command-line options, but check that it
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; doesn't crash. (It crashed formerly on ARM, and proved useful in
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; discovering a bug on PowerPC as well.)
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define i32 @f(i32* %x) nounwind ssp {
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%y = getelementptr inbounds i32* %x, i32 5000
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%tmp103 = load i32* %y, align 4
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ret i32 %tmp103
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}
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50
test/CodeGen/PowerPC/fast-isel-shifter.ll
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50
test/CodeGen/PowerPC/fast-isel-shifter.ll
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@ -0,0 +1,50 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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define i32 @shl() nounwind ssp {
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entry:
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; ELF64: shl
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; ELF64: slw
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%shl = shl i32 -1, 2
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ret i32 %shl
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}
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define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ELF64: shl_reg
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; ELF64: slw
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%shl = shl i32 %src1, %src2
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ret i32 %shl
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}
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define i32 @lshr() nounwind ssp {
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entry:
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; ELF64: lshr
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; ELF64: srw
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%lshr = lshr i32 -1, 2
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ret i32 %lshr
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}
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define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ELF64: lshr_reg
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; ELF64: srw
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%lshr = lshr i32 %src1, %src2
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ret i32 %lshr
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}
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define i32 @ashr() nounwind ssp {
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entry:
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; ELF64: ashr
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; ELF64: srawi
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%ashr = ashr i32 -1, 2
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ret i32 %ashr
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}
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define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
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entry:
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; ELF64: ashr_reg
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; ELF64: sraw
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%ashr = ashr i32 %src1, %src2
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ret i32 %ashr
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}
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