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[AMDGPU] Simplify negated condition
Optimize sequence: %sel = V_CNDMASK_B32_e64 0, 1, %cc %cmp = V_CMP_NE_U32 1, %1 $vcc = S_AND_B64 $exec, %cmp S_CBRANCH_VCC[N]Z => $vcc = S_ANDN2_B64 $exec, %cc S_CBRANCH_VCC[N]Z It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the rebuildSetCC(). Differential Revision: https://reviews.llvm.org/D55402 llvm-svn: 349003
This commit is contained in:
Stanislav Mekhanoshin
parent
f8dd1a7265
commit
198d2e45b0
@ -103,6 +103,122 @@ static MachineInstr* getOrExecSource(const MachineInstr &MI,
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return SaveExecInst;
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}
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// Optimize sequence
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// %sel = V_CNDMASK_B32_e64 0, 1, %cc
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// %cmp = V_CMP_NE_U32 1, %1
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// $vcc = S_AND_B64 $exec, %cmp
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// S_CBRANCH_VCC[N]Z
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// =>
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// $vcc = S_ANDN2_B64 $exec, %cc
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// S_CBRANCH_VCC[N]Z
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//
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// It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
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// rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but
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// only 3 first instructions are really needed. S_AND_B64 with exec is a
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// required part of the pattern since V_CNDMASK_B32 writes zeroes for inactive
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// lanes.
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//
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// Returns %cc register on success.
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static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
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const GCNSubtarget &ST,
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MachineRegisterInfo &MRI,
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LiveIntervals *LIS) {
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const unsigned AndOpc = AMDGPU::S_AND_B64;
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const unsigned Andn2Opc = AMDGPU::S_ANDN2_B64;
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const unsigned CondReg = AMDGPU::VCC;
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const unsigned ExecReg = AMDGPU::EXEC;
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auto I = llvm::find_if(MBB.terminators(), [](const MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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return Opc == AMDGPU::S_CBRANCH_VCCZ ||
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Opc == AMDGPU::S_CBRANCH_VCCNZ; });
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if (I == MBB.terminators().end())
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return AMDGPU::NoRegister;
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auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,
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*I, MRI, LIS);
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if (!And || And->getOpcode() != AndOpc ||
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!And->getOperand(1).isReg() || !And->getOperand(2).isReg())
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return AMDGPU::NoRegister;
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MachineOperand *AndCC = &And->getOperand(1);
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unsigned CmpReg = AndCC->getReg();
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unsigned CmpSubReg = AndCC->getSubReg();
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if (CmpReg == ExecReg) {
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AndCC = &And->getOperand(2);
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CmpReg = AndCC->getReg();
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CmpSubReg = AndCC->getSubReg();
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} else if (And->getOperand(2).getReg() != ExecReg) {
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return AMDGPU::NoRegister;
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}
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auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, MRI, LIS);
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if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||
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Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||
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Cmp->getParent() != And->getParent())
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return AMDGPU::NoRegister;
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MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);
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MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);
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if (Op1->isImm() && Op2->isReg())
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std::swap(Op1, Op2);
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if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
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return AMDGPU::NoRegister;
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unsigned SelReg = Op1->getReg();
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auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS);
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if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
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return AMDGPU::NoRegister;
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Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);
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Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
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MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
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if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
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Op1->getImm() != 0 || Op2->getImm() != 1)
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return AMDGPU::NoRegister;
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LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t'
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<< *Cmp << '\t' << *And);
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unsigned CCReg = CC->getReg();
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LIS->RemoveMachineInstrFromMaps(*And);
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MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
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TII->get(Andn2Opc), And->getOperand(0).getReg())
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.addReg(ExecReg)
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.addReg(CCReg, CC->getSubReg());
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And->eraseFromParent();
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LIS->InsertMachineInstrInMaps(*Andn2);
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LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
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// Try to remove compare. Cmp value should not used in between of cmp
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// and s_and_b64 if VCC or just unused if any other register.
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if ((TargetRegisterInfo::isVirtualRegister(CmpReg) &&
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MRI.use_nodbg_empty(CmpReg)) ||
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(CmpReg == CondReg &&
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std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),
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[TRI, CondReg](const MachineInstr &MI) {
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return MI.readsRegister(CondReg, TRI); }))) {
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LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
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LIS->RemoveMachineInstrFromMaps(*Cmp);
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Cmp->eraseFromParent();
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// Try to remove v_cndmask_b32.
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if (TargetRegisterInfo::isVirtualRegister(SelReg) &&
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MRI.use_nodbg_empty(SelReg)) {
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LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
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LIS->RemoveMachineInstrFromMaps(*Sel);
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Sel->eraseFromParent();
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}
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}
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return CCReg;
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}
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bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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@ -117,6 +233,14 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
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for (MachineBasicBlock &MBB : MF) {
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if (unsigned Reg = optimizeVcndVcmpPair(MBB, ST, MRI, LIS)) {
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RecalcRegs.insert(Reg);
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RecalcRegs.insert(AMDGPU::VCC_LO);
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RecalcRegs.insert(AMDGPU::VCC_HI);
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RecalcRegs.insert(AMDGPU::SCC);
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Changed = true;
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}
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// Try to remove unneeded instructions before s_endpgm.
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if (MBB.succ_empty()) {
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if (MBB.empty())
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@ -18,9 +18,12 @@
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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@ -1599,3 +1602,57 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
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llvm_unreachable("not implemented");
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}
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}
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// Find reaching register definition
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MachineInstr *SIRegisterInfo::findReachingDef(unsigned Reg, unsigned SubReg,
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MachineInstr &Use,
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MachineRegisterInfo &MRI,
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LiveIntervals *LIS) const {
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auto &MDT = LIS->getAnalysis<MachineDominatorTree>();
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SlotIndex UseIdx = LIS->getInstructionIndex(Use);
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SlotIndex DefIdx;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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if (!LIS->hasInterval(Reg))
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return nullptr;
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LiveInterval &LI = LIS->getInterval(Reg);
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LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)
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: MRI.getMaxLaneMaskForVReg(Reg);
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VNInfo *V = nullptr;
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if (LI.hasSubRanges()) {
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for (auto &S : LI.subranges()) {
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if ((S.LaneMask & SubLanes) == SubLanes) {
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V = S.getVNInfoAt(UseIdx);
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break;
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}
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}
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} else {
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V = LI.getVNInfoAt(UseIdx);
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}
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if (!V)
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return nullptr;
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DefIdx = V->def;
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} else {
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// Find last def.
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for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) {
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LiveRange &LR = LIS->getRegUnit(*Units);
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if (VNInfo *V = LR.getVNInfoAt(UseIdx)) {
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if (!DefIdx.isValid() ||
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MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
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LIS->getInstructionFromIndex(V->def)))
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DefIdx = V->def;
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} else {
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return nullptr;
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}
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}
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}
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MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx);
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if (!Def || !MDT.dominates(Def, &Use))
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return nullptr;
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assert(Def->modifiesRegister(Reg, this));
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return Def;
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}
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@ -228,6 +228,12 @@ public:
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getConstrainedRegClassForOperand(const MachineOperand &MO,
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const MachineRegisterInfo &MRI) const override;
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// Find reaching register definition
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MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
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MachineInstr &Use,
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MachineRegisterInfo &MRI,
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LiveIntervals *LIS) const;
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private:
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void buildSpillLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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465
test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
Normal file
465
test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
Normal file
@ -0,0 +1,465 @@
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# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck -check-prefix=GCN %s
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# GCN: name: negated_cond_vop2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_vop3
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_vop2_redef_vcc1
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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# GCN-NEXT: $vcc_lo = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_redef_vcc1
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc_lo = COPY $sgpr0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_vop2_redef_vcc2
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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# GCN-NEXT: $vcc_hi = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop2_redef_vcc2
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc_hi = COPY $sgpr0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_vop3_redef_cmp
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# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
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# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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# GCN-NEXT: %2.sub1:sreg_64_xexec = COPY $sgpr0
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# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_redef_cmp
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body: |
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bb.0:
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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%2.sub1 = COPY $sgpr0
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_undef_vcc
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# GCN: $vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_undef_vcc
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body: |
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bb.0:
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$vcc = S_AND_B64 $exec, undef $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
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bb.2:
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S_ENDPGM
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...
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# GCN: name: negated_cond_vop3_imp_vcc
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# GCN: $vcc = IMPLICIT_DEF
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# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
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# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
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---
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name: negated_cond_vop3_imp_vcc
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, $vcc, implicit $exec
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%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
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$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
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S_BRANCH %bb.1
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bb.1:
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S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_imp_vcc
|
||||
# GCN: $vcc = IMPLICIT_DEF
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, $vcc, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_imp_vcc
|
||||
body: |
|
||||
bb.0:
|
||||
$vcc = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, $vcc, implicit $exec
|
||||
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
$vcc = S_AND_B64 killed $vcc, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_redef_sel
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: %1:vgpr_32 = COPY $vgpr0
|
||||
# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
||||
# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_redef_sel
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%1:vgpr_32 = COPY $vgpr0
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_used_sel
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_used_sel
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
$vgpr0 = COPY %1
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_used_vcc
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
# GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_used_vcc
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
$sgpr0_sgpr1 = COPY $vcc
|
||||
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_sel_wrong_subreg1
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
|
||||
# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_sel_wrong_subreg1
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1.sub1 = IMPLICIT_DEF
|
||||
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_sel_wrong_subreg2
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
|
||||
# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_sel_wrong_subreg2
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%1.sub1 = IMPLICIT_DEF
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_sel_right_subreg1
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_sel_right_subreg1
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1.sub1 = IMPLICIT_DEF
|
||||
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_sel_right_subreg2
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_sel_right_subreg2
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%1.sub1 = IMPLICIT_DEF
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub0, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop3_sel_subreg_overlap
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1.sub2:vreg_128 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN-NEXT: %1.sub2_sub3:vreg_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
|
||||
# GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop3_sel_subreg_overlap
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1.sub2:vreg_128 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%1.sub2_sub3 = IMPLICIT_DEF
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec
|
||||
$vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
S_BRANCH %bb.0
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_dominated_blocks
|
||||
# GCN: %0:sreg_64_xexec = IMPLICIT_DEF
|
||||
# GCN: $vcc = S_ANDN2_B64 $exec, %0, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_dominated_blocks
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
|
||||
bb.1:
|
||||
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.2:
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.3:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_different_blocks_cmp_and
|
||||
# GCN: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
# GCN: $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_different_blocks_cmp_and
|
||||
body: |
|
||||
bb.0:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
%2:sreg_64_xexec = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
||||
|
||||
bb.1:
|
||||
$vcc = S_AND_B64 $exec, killed %2, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.2:
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.3:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
||||
# GCN: name: negated_cond_vop2_not_dominated_blocks
|
||||
# GCN: V_CNDMASK_B32_e64 0, 1,
|
||||
# GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc
|
||||
---
|
||||
name: negated_cond_vop2_not_dominated_blocks
|
||||
body: |
|
||||
bb.0:
|
||||
$vcc = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
%0:sreg_64_xexec = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %0, implicit $exec
|
||||
|
||||
bb.2:
|
||||
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
|
||||
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
|
||||
S_BRANCH %bb.3
|
||||
|
||||
bb.3:
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.4:
|
||||
S_ENDPGM
|
||||
...
|
||||
75
test/CodeGen/AMDGPU/optimize-negated-cond.ll
Normal file
75
test/CodeGen/AMDGPU/optimize-negated-cond.ll
Normal file
@ -0,0 +1,75 @@
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}negated_cond:
|
||||
; GCN: BB0_1:
|
||||
; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],
|
||||
; GCN: BB0_2:
|
||||
; GCN-NOT: v_cndmask_b32
|
||||
; GCN-NOT: v_cmp
|
||||
; GCN: s_andn2_b64 vcc, exec, [[CC]]
|
||||
; GCN: s_cbranch_vccnz BB0_4
|
||||
define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) {
|
||||
bb:
|
||||
br label %bb1
|
||||
|
||||
bb1:
|
||||
%tmp1 = load i32, i32 addrspace(1)* %arg1
|
||||
%tmp2 = icmp eq i32 %tmp1, 0
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%tmp3 = phi i32 [ 0, %bb1 ], [ %tmp6, %bb4 ]
|
||||
%tmp4 = shl i32 %tmp3, 5
|
||||
br i1 %tmp2, label %bb3, label %bb4
|
||||
|
||||
bb3:
|
||||
%tmp5 = add i32 %tmp4, 1
|
||||
br label %bb4
|
||||
|
||||
bb4:
|
||||
%tmp6 = phi i32 [ %tmp5, %bb3 ], [ %tmp4, %bb2 ]
|
||||
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp6
|
||||
store i32 0, i32 addrspace(1)* %gep
|
||||
%tmp7 = icmp eq i32 %tmp6, 32
|
||||
br i1 %tmp7, label %bb1, label %bb2
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
|
||||
; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],
|
||||
; GCN: BB1_1:
|
||||
; GCN-NOT: v_cndmask_b32
|
||||
; GCN-NOT: v_cmp
|
||||
; GCN: s_andn2_b64 vcc, exec, [[CC]]
|
||||
; GCN: s_cbranch_vccz BB1_3
|
||||
define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) {
|
||||
bb:
|
||||
br label %bb2
|
||||
|
||||
bb2:
|
||||
%tmp1 = load i32, i32 addrspace(1)* %arg1
|
||||
%tmp2 = icmp eq i32 %tmp1, 0
|
||||
br label %bb4
|
||||
|
||||
bb3:
|
||||
ret void
|
||||
|
||||
bb4:
|
||||
%tmp3 = phi i32 [ 0, %bb2 ], [ %tmp7, %bb7 ]
|
||||
%tmp4 = shl i32 %tmp3, 5
|
||||
br i1 %tmp2, label %bb5, label %bb6
|
||||
|
||||
bb5:
|
||||
%tmp5 = add i32 %tmp4, 1
|
||||
br label %bb7
|
||||
|
||||
bb6:
|
||||
%tmp6 = add i32 %tmp3, 1
|
||||
br label %bb7
|
||||
|
||||
bb7:
|
||||
%tmp7 = phi i32 [ %tmp5, %bb5 ], [ %tmp6, %bb6 ]
|
||||
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp7
|
||||
store i32 0, i32 addrspace(1)* %gep
|
||||
%tmp8 = icmp eq i32 %tmp7, 32
|
||||
br i1 %tmp8, label %bb3, label %bb4
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user