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GlobalISel: Implement narrowing for G_STORE

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Legalize stores of types that are too wide by breaking them up into
sequences of smaller stores.

llvm-svn: 292412
This commit is contained in:
Justin Bogner 2017-01-18 17:29:54 +00:00
parent 4fda119cb0
commit 19a6ba7a53
2 changed files with 35 additions and 2 deletions
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25
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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@ -125,6 +125,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
// FIXME: Don't know how to handle secondary types yet.
if (TypeIdx != 0)
return UnableToLegalize;
MIRBuilder.setInstr(MI);
switch (MI.getOpcode()) {
default:
return UnableToLegalize;
@ -134,8 +137,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
NarrowTy.getSizeInBits();
MIRBuilder.setInstr(MI);
SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
SmallVector<uint64_t, 2> Indexes;
extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
@ -160,6 +161,26 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
MI.eraseFromParent();
return Legalized;
}
case TargetOpcode::G_STORE: {
unsigned NarrowSize = NarrowTy.getSizeInBits();
int NumParts =
MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
LLT NarrowPtrTy = LLT::pointer(
MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
SmallVector<unsigned, 2> SrcRegs;
extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
for (int i = 0; i < NumParts; ++i) {
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
MIRBuilder.buildGEP(DstReg, MI.getOperand(1).getReg(), Offset);
MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
}
MI.eraseFromParent();
return Legalized;
}
}
}

12
test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
View File

@ -62,6 +62,8 @@ registers:
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@ -92,4 +94,14 @@ body: |
; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0
; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64)
; CHECK: G_STORE %5(s64), [[GEP0]](p0) :: (store 16 into %ir.addr)
; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr)
%6(s64) = G_PTRTOINT %0(p0)
%7(s128) = G_SEQUENCE %5, 0, %6, 64
G_STORE %7, %0 :: (store 16 into %ir.addr)
...