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Revert "[misched] Extend scheduler to handle unsupported features"

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This reverts commit r273551.

Patch contained a wrong check for isUnsupported.

llvm-svn: 273565
This commit is contained in:
Simon Dardis 2016-06-23 14:54:47 +00:00
parent 4edfb012af
commit 19be77fb82
3 changed files with 1 additions and 53 deletions
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16
include/llvm/Target/TargetSchedule.td
View File

@ -55,8 +55,6 @@ include "llvm/Target/TargetItinerary.td"
class Instruction; // Forward def
class Predicate; // Forward def
// DAG operator that interprets the DAG args as Instruction defs.
def instrs;
@ -99,20 +97,6 @@ class SchedMachineModel {
// resulting from changes to the instruction definitions.
bit CompleteModel = 1;
// A processor may only implement part of published ISA, due to either new ISA
// extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
// (ARM/MIPS/PowerPC/SPARC soft float cores).
//
// For a processor which doesn't support some feature(s), the schedule model
// can use:
//
// let<Predicate> UnsupportedFeatures = [HaveA,..,HaveY];
//
// to skip the checks for scheduling information when building LLVM for
// instructions which have any of the listed predicates in their Predicates
// field.
list<Predicate> UnsupportedFeatures = [];
bit NoModel = 0; // Special tag to indicate missing machine model.
}

30
utils/TableGen/CodeGenSchedule.cpp
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@ -120,10 +120,6 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
// (For per-operand resources mapped to itinerary classes).
collectProcItinRW();
// Find UnsupportedFeatures records for each processor.
// (For per-operand resources mapped to itinerary classes).
collectProcUnsupportedFeatures();
// Infer new SchedClasses from SchedVariant.
inferSchedClasses();
@ -833,15 +829,6 @@ void CodeGenSchedModels::collectProcItinRW() {
}
}
// Gather the unsupported features for processor models.
void CodeGenSchedModels::collectProcUnsupportedFeatures() {
for (CodeGenProcModel &ProcModel : ProcModels) {
for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) {
ProcModel.UnsupportedFeaturesDefs.push_back(Pred);
}
}
}
/// Infer new classes from existing classes. In the process, this may create new
/// SchedWrites from sequences of existing SchedWrites.
void CodeGenSchedModels::inferSchedClasses() {
@ -1553,8 +1540,6 @@ void CodeGenSchedModels::checkCompleteness() {
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
if (Inst->hasNoSchedulingInfo)
continue;
if (ProcModel.isUnsupported(*Inst))
continue;
unsigned SCIdx = getSchedClassIdx(*Inst);
if (!SCIdx) {
if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
@ -1590,10 +1575,7 @@ void CodeGenSchedModels::checkCompleteness() {
<< "- Consider setting 'CompleteModel = 0' while developing new models.\n"
<< "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
<< "- Instructions should usually have Sched<[...]> as a superclass, "
"you may temporarily use an empty list.\n"
<< "- Instructions related to unsupported features can be excluded with "
"list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
"processor model.\n\n";
"you may temporarily use an empty list.\n\n";
PrintFatalError("Incomplete schedule model");
}
}
@ -1774,16 +1756,6 @@ unsigned CodeGenProcModel::getProcResourceIdx(Record *PRDef) const {
return 1 + (PRPos - ProcResourceDefs.begin());
}
bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
for (const Record *TheDef : UnsupportedFeaturesDefs) {
for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
if (TheDef->getName() == PredDef->getName())
return true;
}
}
return false;
}
#ifndef NDEBUG
void CodeGenProcModel::dump() const {
dbgs() << Index << ": " << ModelName << " "

8
utils/TableGen/CodeGenSchedule.h
View File

@ -189,10 +189,6 @@ struct CodeGenProcModel {
// This list is empty if no ItinRW refers to this Processor.
RecVec ItinRWDefs;
// List of unsupported feature.
// This list is empty if the Processor has no UnsupportedFeatures.
RecVec UnsupportedFeaturesDefs;
// All read/write resources associated with this processor.
RecVec WriteResDefs;
RecVec ReadAdvanceDefs;
@ -215,8 +211,6 @@ struct CodeGenProcModel {
unsigned getProcResourceIdx(Record *PRDef) const;
bool isUnsupported(const CodeGenInstruction &Inst) const;
#ifndef NDEBUG
void dump() const;
#endif
@ -408,8 +402,6 @@ private:
void collectProcItinRW();
void collectProcUnsupportedFeatures();
void inferSchedClasses();
void checkCompleteness();