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add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it

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llvm-svn: 23726
This commit is contained in:
Chris Lattner 2005-10-14 04:55:10 +00:00
parent d83bbd0f14
commit 1a001d068a
1 changed files with 13 additions and 0 deletions
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13
lib/Target/TargetSelectionDAG.td
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@ -45,6 +45,10 @@ class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
int OtherOperandNum = OtherOp; int OtherOperandNum = OtherOp;
} }
class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
int BigOperandNum = BigOp;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Selection DAG Type Profile definitions. // Selection DAG Type Profile definitions.
// //
@ -77,6 +81,12 @@ def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
SDTCisSameAs<0, 1>, SDTCisFP<0> SDTCisSameAs<0, 1>, SDTCisFP<0>
]>; ]>;
def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
]>;
def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
]>;
def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
SDTCisVTSmallerThanOp<2, 1> SDTCisVTSmallerThanOp<2, 1>
@ -136,6 +146,9 @@ def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;