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push fast-math check for machine-combiner reassociations into instruction-type check; NFC
This makes it simpler to add instruction types that don't depend on fast-math. llvm-svn: 243596
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@ -6348,8 +6348,8 @@ static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
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// TODO: There are many more machine instruction opcodes to match:
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// TODO: There are many more machine instruction opcodes to match:
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// 1. Other data types (integer, vectors)
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// 1. Other data types (integer, vectors)
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// 2. Other math / logic operations (and, or)
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// 2. Other math / logic operations (and, or)
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static bool isAssociativeAndCommutative(unsigned Opcode) {
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static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
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switch (Opcode) {
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switch (Inst.getOpcode()) {
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case X86::ADDSDrr:
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case X86::ADDSDrr:
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case X86::ADDSSrr:
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case X86::ADDSSrr:
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case X86::VADDSDrr:
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case X86::VADDSDrr:
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@ -6358,7 +6358,7 @@ static bool isAssociativeAndCommutative(unsigned Opcode) {
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case X86::MULSSrr:
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case X86::MULSSrr:
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case X86::VMULSDrr:
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case X86::VMULSDrr:
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case X86::VMULSSrr:
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case X86::VMULSSrr:
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return true;
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return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
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default:
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default:
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return false;
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return false;
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}
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}
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@ -6374,7 +6374,7 @@ static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
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// 2. The instruction must have virtual register definitions for its
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// 2. The instruction must have virtual register definitions for its
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// operands in the same basic block.
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// operands in the same basic block.
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// 3. The instruction must have a reassociable sibling.
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// 3. The instruction must have a reassociable sibling.
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if (isAssociativeAndCommutative(Inst.getOpcode()) &&
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if (isAssociativeAndCommutative(Inst) &&
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hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
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hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
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hasReassocSibling(Inst, Commuted))
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hasReassocSibling(Inst, Commuted))
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return true;
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return true;
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@ -6391,9 +6391,6 @@ static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
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// that pattern.
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// that pattern.
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bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
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bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
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if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
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return false;
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// TODO: There is nothing x86-specific here except the instruction type.
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// TODO: There is nothing x86-specific here except the instruction type.
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// This logic could be hoisted into the machine combiner pass itself.
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// This logic could be hoisted into the machine combiner pass itself.
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