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[ARM][ParallelDSP] Disable for big-endian
Bail early when we don't have a preheader and also if the target is big endian because it's written with only little endian in mind! Differential Revision: https://reviews.llvm.org/D59368 llvm-svn: 356243
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@ -201,6 +201,12 @@ namespace {
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return false;
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}
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// We need a preheader as getIncomingValueForBlock assumes there is one.
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if (!TheLoop->getLoopPreheader()) {
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LLVM_DEBUG(dbgs() << "No preheader found, bailing out\n");
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return false;
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}
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Function &F = *Header->getParent();
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M = F.getParent();
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DL = &M->getDataLayout();
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@ -220,6 +226,12 @@ namespace {
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return false;
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}
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if (!ST->isLittle()) {
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LLVM_DEBUG(dbgs() << "Only supporting little endian: not running pass "
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"ARMParallelDSP\n");
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return false;
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}
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LoopAccessInfo LAI(L, SE, TLI, AA, DT, LI);
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LLVM_DEBUG(dbgs() << "\n== Parallel DSP pass ==\n");
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@ -454,12 +466,6 @@ static void MatchReductions(Function &F, Loop *TheLoop, BasicBlock *Header,
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F.getFnAttribute("no-nans-fp-math").getValueAsString() == "true";
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const BasicBlock *Latch = TheLoop->getLoopLatch();
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// We need a preheader as getIncomingValueForBlock assumes there is one.
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if (!TheLoop->getLoopPreheader()) {
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LLVM_DEBUG(dbgs() << "No preheader found, bailing out\n");
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return;
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}
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for (PHINode &Phi : Header->phis()) {
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const auto *Ty = Phi.getType();
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if (!Ty->isIntegerTy(32) && !Ty->isIntegerTy(64))
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@ -1,4 +1,7 @@
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; RUN: llc -O3 -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s | FileCheck %s
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; RUN: llc -O3 -mtriple=armeb-arm-eabi -mcpu=cortex-m33 < %s | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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; CHECK-UNSUPPORTED-NOT: smlad
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; CHECK-LABEL: add_user
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; CHECK: %for.body
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@ -1,4 +1,5 @@
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
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; RUN: opt -mtriple=armeb-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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;
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; The Cortex-M0 does not support unaligned accesses:
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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@ -1,6 +1,7 @@
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; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -arm-parallel-dsp %s -S -o - | FileCheck %s
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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; RUN: opt -mtriple=armeb-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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define i32 @smladx(i16* nocapture readonly %pIn1, i16* nocapture readonly %pIn2, i32 %j, i32 %limit) {
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@ -1,4 +1,5 @@
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
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; RUN: opt -mtriple=armeb-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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;
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; The Cortex-M0 does not support unaligned accesses:
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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@ -1,9 +1,14 @@
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; RUN: llc -O3 -mtriple=thumbv7em %s -o - | FileCheck %s
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; RUN: llc -O3 -mtriple=thumbv7eb %s -o - | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
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; RUN: llc -O3 -mtriple=thumbv8m.main -mattr=+dsp %s -o - | FileCheck %s
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; CHECK-UNSUPPORTED-LABEL: unroll_n_jam_smlad
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; CHECK-UNSUPPORTED-NOT: smlad r{{.}}
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; Test that the duplicate loads are removed, which allows parallel dsp to find
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; the parallel operations.
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; CHECK-LABEL: unroll_n_jam_smlad
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define void @unroll_n_jam_smlad(i32* %res, i16* %A, i16* %B, i32 %N, i32 %idx) {
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entry:
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%xtraiter306.i = and i32 %N, 3
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