mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 12:02:58 +02:00
Sink queries into asserts since the variable is unused otherwise.
llvm-svn: 227836
This commit is contained in:
parent
439bf9404e
commit
1a48904da5
@ -68,7 +68,6 @@ char HexagonExpandPredSpillCode::ID = 0;
|
||||
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
|
||||
|
||||
const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
|
||||
const HexagonRegisterInfo *TRI = QST.getRegisterInfo();
|
||||
const HexagonInstrInfo *TII = QST.getInstrInfo();
|
||||
|
||||
// Loop over all of the basic blocks.
|
||||
@ -83,7 +82,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
|
||||
if (Opc == Hexagon::STriw_pred) {
|
||||
// STriw_pred [R30], ofst, SrcReg;
|
||||
unsigned FP = MI->getOperand(0).getReg();
|
||||
assert(FP == TRI->getFrameRegister() &&
|
||||
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
|
||||
"Not a Frame Pointer, Nor a Spill Slot");
|
||||
assert(MI->getOperand(1).isImm() && "Not an offset");
|
||||
int Offset = MI->getOperand(1).getImm();
|
||||
@ -130,7 +129,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
|
||||
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
|
||||
"Not a predicate register");
|
||||
unsigned FP = MI->getOperand(1).getReg();
|
||||
assert(FP == TRI->getFrameRegister() &&
|
||||
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
|
||||
"Not a Frame Pointer, Nor a Spill Slot");
|
||||
assert(MI->getOperand(2).isImm() && "Not an offset");
|
||||
int Offset = MI->getOperand(2).getImm();
|
||||
|
Loading…
Reference in New Issue
Block a user