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AMDGPU/GlobalISel: Replace handling of boolean values
This solves selection failures with generated selection patterns, which would fail due to inferring the SGPR reg bank for virtual registers with a set register class instead of VCC bank. Use instruction selection would constrain the virtual register to a specific class, so when the def was selected later the bank no longer was set to VCC. Remove the SCC reg bank. SCC isn't directly addressable, so it requires copying from SCC to an allocatable 32-bit register during selection, so these might as well be treated as 32-bit SGPR values. Now any scalar boolean value that will produce an outupt in SCC should be widened during RegBankSelect to s32. Any s1 value should be a vector boolean during selection. This makes the vcc register bank unambiguous with a normal SGPR during selection. Summary of how this should now work: - G_TRUNC is always a no-op, and never should use a vcc bank result. - SALU boolean operations should be promoted to s32 in RegBankSelect apply mapping - An s1 value means vcc bank at selection. The exception is for legalization artifacts that use s1, which are never VCC. All other contexts should infer the VCC register classes for s1 typed registers. The LLT for the register is now needed to infer the correct register class. Extensions with vcc sources should be legalized to a select of constants during RegBankSelect. - Copy from non-vcc to vcc ensures high bits of the input value are cleared during selection. - SALU boolean inputs should ensure the inputs are 0/1. This includes select, conditional branches, and carry-ins. There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT selection ignores the usual register-bank from register class functions, and can't handle truncates with VCC result banks. I think this is OK, since the artifacts are specially treated anyway. This does require some care to avoid producing cases with vcc. There will also be no 100% reliable way to verify this rule is followed in selection in case of register classes, and violations manifests themselves as invalid copy instructions much later. Standard phi handling also only considers the bank of the result register, and doesn't insert copies to make the source banks match. This doesn't work for vcc, so we have to manually correct phi inputs in this case. We should add a verifier check to make sure there are no phis with mixed vcc and non-vcc register bank inputs. There's also some duplication with the LegalizerHelper, and some code which should live in the helper. I don't see a good way to share special knowledge about what types to use for intermediate operations depending on the bank for example. Using the helper to replace extensions with selects also seems somewhat awkward to me. Another issue is there are some contexts calling getRegBankFromRegClass that apparently don't have the LLT type for the register, but I haven't yet run into a real issue from this. This also introduces new unnecessary instructions in most cases, since we don't yet try to optimize out the zext when the source is known to come from a compare.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
8defb1c20e
commit
1a53e6403d
@ -15,35 +15,34 @@ namespace AMDGPU {
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enum PartialMappingIdx {
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None = - 1,
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PM_SGPR1 = 2,
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PM_SGPR16 = 6,
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PM_SGPR32 = 7,
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PM_SGPR64 = 8,
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PM_SGPR128 = 9,
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PM_SGPR256 = 10,
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PM_SGPR512 = 11,
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PM_SGPR1024 = 12,
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PM_VGPR1 = 13,
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PM_VGPR16 = 17,
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PM_VGPR32 = 18,
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PM_VGPR64 = 19,
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PM_VGPR128 = 20,
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PM_VGPR256 = 21,
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PM_VGPR512 = 22,
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PM_VGPR1024 = 23,
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PM_SGPR96 = 24,
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PM_VGPR96 = 25,
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PM_AGPR96 = 26,
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PM_AGPR32 = 32,
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PM_AGPR64 = 33,
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PM_AGPR128 = 34,
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PM_AGPR512 = 36,
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PM_AGPR1024 = 37
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PM_SGPR1 = 1,
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PM_SGPR16 = 5,
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PM_SGPR32 = 6,
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PM_SGPR64 = 7,
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PM_SGPR128 = 8,
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PM_SGPR256 = 9,
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PM_SGPR512 = 10,
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PM_SGPR1024 = 11,
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PM_VGPR1 = 12,
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PM_VGPR16 = 16,
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PM_VGPR32 = 17,
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PM_VGPR64 = 18,
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PM_VGPR128 = 19,
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PM_VGPR256 = 20,
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PM_VGPR512 = 21,
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PM_VGPR1024 = 22,
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PM_SGPR96 = 23,
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PM_VGPR96 = 24,
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PM_AGPR96 = 25,
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PM_AGPR32 = 31,
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PM_AGPR64 = 32,
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PM_AGPR128 = 33,
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PM_AGPR512 = 34,
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PM_AGPR1024 = 35
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};
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const RegisterBankInfo::PartialMapping PartMappings[] {
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// StartIdx, Length, RegBank
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{0, 1, SCCRegBank},
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{0, 1, VCCRegBank},
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{0, 1, SGPRRegBank}, // SGPR begin
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@ -75,40 +74,37 @@ const RegisterBankInfo::PartialMapping PartMappings[] {
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};
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const RegisterBankInfo::ValueMapping ValMappings[] {
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// SCC
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// VCC
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{&PartMappings[0], 1},
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// VCC
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{&PartMappings[1], 1},
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// SGPRs
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{&PartMappings[2], 1}, // 1
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{&PartMappings[1], 1}, // 1
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{nullptr, 0}, // Illegal power of 2 sizes
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{nullptr, 0},
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{nullptr, 0},
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{&PartMappings[3], 1}, // 16
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{&PartMappings[4], 1}, // 32
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{&PartMappings[5], 1}, // 64
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{&PartMappings[6], 1}, // 128
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{&PartMappings[7], 1}, // 256
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{&PartMappings[8], 1}, // 512
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{&PartMappings[9], 1}, // 1024
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{&PartMappings[2], 1}, // 16
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{&PartMappings[3], 1}, // 32
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{&PartMappings[4], 1}, // 64
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{&PartMappings[5], 1}, // 128
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{&PartMappings[6], 1}, // 256
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{&PartMappings[7], 1}, // 512
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{&PartMappings[8], 1}, // 1024
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// VGPRs
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{&PartMappings[10], 1}, // 1
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{&PartMappings[9], 1}, // 1
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{nullptr, 0},
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{nullptr, 0},
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{nullptr, 0},
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{&PartMappings[11], 1}, // 16
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{&PartMappings[12], 1}, // 32
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{&PartMappings[13], 1}, // 64
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{&PartMappings[14], 1}, // 128
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{&PartMappings[15], 1}, // 256
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{&PartMappings[16], 1}, // 512
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{&PartMappings[17], 1}, // 1024
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{&PartMappings[10], 1}, // 16
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{&PartMappings[11], 1}, // 32
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{&PartMappings[12], 1}, // 64
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{&PartMappings[13], 1}, // 128
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{&PartMappings[14], 1}, // 256
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{&PartMappings[15], 1}, // 512
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{&PartMappings[16], 1}, // 1024
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{&PartMappings[17], 1},
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{&PartMappings[18], 1},
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{&PartMappings[19], 1},
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{&PartMappings[20], 1},
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// AGPRs
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{nullptr, 0},
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@ -116,12 +112,12 @@ const RegisterBankInfo::ValueMapping ValMappings[] {
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{nullptr, 0},
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{nullptr, 0},
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{nullptr, 0},
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{&PartMappings[21], 1}, // 32
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{&PartMappings[22], 1}, // 64
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{&PartMappings[23], 1}, // 128
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{&PartMappings[20], 1}, // 32
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{&PartMappings[21], 1}, // 64
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{&PartMappings[22], 1}, // 128
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{nullptr, 0},
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{&PartMappings[24], 1}, // 512
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{&PartMappings[25], 1} // 1024
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{&PartMappings[23], 1}, // 512
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{&PartMappings[24], 1} // 1024
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};
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const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
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@ -147,10 +143,9 @@ const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
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};
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enum ValueMappingIdx {
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SCCStartIdx = 0,
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SGPRStartIdx = 2,
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VGPRStartIdx = 13,
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AGPRStartIdx = 27
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SGPRStartIdx = 1,
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VGPRStartIdx = 12,
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AGPRStartIdx = 26
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};
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const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
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@ -158,12 +153,9 @@ const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
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unsigned Idx;
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switch (Size) {
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case 1:
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if (BankID == AMDGPU::SCCRegBankID)
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return &ValMappings[0];
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if (BankID == AMDGPU::VCCRegBankID)
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return &ValMappings[1];
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return &ValMappings[0];
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// 1-bit values not from a compare etc.
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Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
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break;
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case 96:
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@ -70,28 +70,6 @@ void AMDGPUInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits &KB,
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InstructionSelector::setupMF(MF, KB, CoverageInfo);
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}
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static bool isSCC(Register Reg, const MachineRegisterInfo &MRI) {
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if (Register::isPhysicalRegister(Reg))
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return Reg == AMDGPU::SCC;
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auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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const TargetRegisterClass *RC =
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RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
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if (RC) {
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// FIXME: This is ambiguous for wave32. This could be SCC or VCC, but the
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// context of the register bank has been lost.
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// Has a hack getRegClassForSizeOnBank uses exactly SGPR_32RegClass, which
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// won't ever beconstrained any further.
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if (RC != &AMDGPU::SGPR_32RegClass)
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return false;
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const LLT Ty = MRI.getType(Reg);
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return Ty.isValid() && Ty.getSizeInBits() == 1;
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}
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const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
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return RB->getID() == AMDGPU::SCCRegBankID;
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}
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bool AMDGPUInstructionSelector::isVCC(Register Reg,
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const MachineRegisterInfo &MRI) const {
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if (Register::isPhysicalRegister(Reg))
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@ -134,12 +112,26 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
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return false;
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const TargetRegisterClass *SrcRC
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= TRI.getConstrainedRegClassForOperand(Src, *MRI);
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Register MaskedReg = MRI->createVirtualRegister(SrcRC);
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// We can't trust the high bits at this point, so clear them.
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// TODO: Skip masking high bits if def is known boolean.
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unsigned AndOpc = TRI.isSGPRClass(SrcRC) ?
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AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;
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BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg)
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.addImm(1)
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.addReg(SrcReg);
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
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.addImm(0)
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.addReg(SrcReg);
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.addReg(MaskedReg);
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if (!MRI->getRegClassOrNull(SrcReg))
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MRI->setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, *MRI));
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MRI->setRegClass(SrcReg, SrcRC);
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I.eraseFromParent();
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return true;
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}
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@ -196,11 +188,6 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
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}
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const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
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if (RB.getID() == AMDGPU::SCCRegBankID) {
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LLVM_DEBUG(dbgs() << "illegal scc phi\n");
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return false;
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}
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DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI);
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if (!DefRC) {
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LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
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@ -208,6 +195,7 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
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}
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}
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// TODO: Verify that all registers have the same bank
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I.setDesc(TII.get(TargetOpcode::PHI));
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return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);
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}
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@ -407,7 +395,7 @@ bool AMDGPUInstructionSelector::selectG_UADDO_USUBO(MachineInstr &I) const {
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Register Dst1Reg = I.getOperand(1).getReg();
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const bool IsAdd = I.getOpcode() == AMDGPU::G_UADDO;
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if (!isSCC(Dst1Reg, *MRI)) {
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if (isVCC(Dst1Reg, *MRI)) {
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// The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
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// carry out despite the _i32 name. These were renamed in VI to _U32.
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// FIXME: We should probably rename the opcodes here.
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@ -742,7 +730,7 @@ bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const {
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auto Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
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Register CCReg = I.getOperand(0).getReg();
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if (isSCC(CCReg, *MRI)) {
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if (!isVCC(CCReg, *MRI)) {
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int Opcode = getS_CMPOpcode(Pred, Size);
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if (Opcode == -1)
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return false;
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@ -1085,7 +1073,7 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
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assert(Size <= 32 || Size == 64);
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const MachineOperand &CCOp = I.getOperand(1);
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Register CCReg = CCOp.getReg();
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if (isSCC(CCReg, *MRI)) {
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if (!isVCC(CCReg, *MRI)) {
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unsigned SelectOpcode = Size == 64 ? AMDGPU::S_CSELECT_B64 :
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AMDGPU::S_CSELECT_B32;
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MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
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@ -1157,10 +1145,19 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
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if (!DstTy.isScalar())
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return false;
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const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
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const LLT S1 = LLT::scalar(1);
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const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
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if (SrcRB != DstRB)
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return false;
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const RegisterBank *DstRB;
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if (DstTy == S1) {
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// This is a special case. We don't treat s1 for legalization artifacts as
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// vcc booleans.
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DstRB = SrcRB;
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} else {
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DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
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if (SrcRB != DstRB)
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return false;
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}
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unsigned DstSize = DstTy.getSizeInBits();
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unsigned SrcSize = SrcTy.getSizeInBits();
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@ -1201,6 +1198,20 @@ static bool shouldUseAndMask(unsigned Size, unsigned &Mask) {
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return SignedMask >= -16 && SignedMask <= 64;
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}
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// Like RegisterBankInfo::getRegBank, but don't assume vcc for s1.
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const RegisterBank *AMDGPUInstructionSelector::getArtifactRegBank(
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Register Reg, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const {
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const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
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return RB;
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// Ignore the type, since we don't use vcc in artifacts.
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if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
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return &RBI.getRegBankFromRegClass(*RC, LLT());
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return nullptr;
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}
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bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
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bool Signed = I.getOpcode() == AMDGPU::G_SEXT;
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const DebugLoc &DL = I.getDebugLoc();
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@ -1210,57 +1221,17 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
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const LLT DstTy = MRI->getType(DstReg);
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const LLT SrcTy = MRI->getType(SrcReg);
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const LLT S1 = LLT::scalar(1);
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const unsigned SrcSize = SrcTy.getSizeInBits();
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const unsigned DstSize = DstTy.getSizeInBits();
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if (!DstTy.isScalar())
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return false;
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const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
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if (SrcBank->getID() == AMDGPU::SCCRegBankID) {
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if (SrcTy != S1 || DstSize > 64) // Invalid
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return false;
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unsigned Opcode =
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DstSize > 32 ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
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const TargetRegisterClass *DstRC =
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DstSize > 32 ? &AMDGPU::SReg_64RegClass : &AMDGPU::SReg_32RegClass;
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// FIXME: Create an extra copy to avoid incorrectly constraining the result
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// of the scc producer.
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Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg)
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.addReg(SrcReg);
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BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
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.addReg(TmpReg);
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// The instruction operands are backwards from what you would expect.
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BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
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.addImm(0)
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.addImm(Signed ? -1 : 1);
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I.eraseFromParent();
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return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);
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}
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if (SrcBank->getID() == AMDGPU::VCCRegBankID && DstSize <= 32) {
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if (SrcTy != S1) // Invalid
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return false;
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MachineInstr *ExtI =
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BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
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.addImm(0) // src0_modifiers
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.addImm(0) // src0
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.addImm(0) // src1_modifiers
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.addImm(Signed ? -1 : 1) // src1
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.addUse(SrcReg);
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
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}
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if (I.getOpcode() == AMDGPU::G_ANYEXT)
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return selectCOPY(I);
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// Artifact casts should never use vcc.
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const RegisterBank *SrcBank = getArtifactRegBank(SrcReg, *MRI, TRI);
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if (SrcBank->getID() == AMDGPU::VGPRRegBankID && DstSize <= 32) {
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// 64-bit should have been split up in RegBankSelect
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@ -1512,12 +1483,15 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
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// GlobalISel, we should push that decision into RegBankSelect. Assume for now
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// RegBankSelect knows what it's doing if the branch condition is scc, even
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// though it currently does not.
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if (isSCC(CondReg, *MRI)) {
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if (!isVCC(CondReg, *MRI)) {
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if (MRI->getType(CondReg) != LLT::scalar(32))
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return false;
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CondPhysReg = AMDGPU::SCC;
|
||||
BrOpcode = AMDGPU::S_CBRANCH_SCC1;
|
||||
// FIXME: Hack for isSCC tests
|
||||
ConstrainRC = &AMDGPU::SGPR_32RegClass;
|
||||
} else if (isVCC(CondReg, *MRI)) {
|
||||
} else {
|
||||
// FIXME: Do we have to insert an and with exec here, like in SelectionDAG?
|
||||
// We sort of know that a VCC producer based on the register bank, that ands
|
||||
// inactive lanes with 0. What if there was a logical operation with vcc
|
||||
@ -1526,8 +1500,7 @@ bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
|
||||
CondPhysReg = TRI.getVCC();
|
||||
BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;
|
||||
ConstrainRC = TRI.getBoolRC();
|
||||
} else
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!MRI->getRegClassOrNull(CondReg))
|
||||
MRI->setRegClass(CondReg, ConstrainRC);
|
||||
|
||||
@ -38,6 +38,7 @@ class MachineInstr;
|
||||
class MachineIRBuilder;
|
||||
class MachineOperand;
|
||||
class MachineRegisterInfo;
|
||||
class RegisterBank;
|
||||
class SIInstrInfo;
|
||||
class SIMachineFunctionInfo;
|
||||
class SIRegisterInfo;
|
||||
@ -69,6 +70,10 @@ private:
|
||||
bool isInstrUniform(const MachineInstr &MI) const;
|
||||
bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
|
||||
|
||||
const RegisterBank *getArtifactRegBank(
|
||||
Register Reg, const MachineRegisterInfo &MRI,
|
||||
const TargetRegisterInfo &TRI) const;
|
||||
|
||||
/// tblgen-erated 'select' implementation.
|
||||
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
|
||||
|
||||
|
||||
@ -244,7 +244,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
S32, S64, S16, V2S16
|
||||
};
|
||||
|
||||
setAction({G_BRCOND, S1}, Legal);
|
||||
setAction({G_BRCOND, S1}, Legal); // VCC branches
|
||||
setAction({G_BRCOND, S32}, Legal); // SCC branches
|
||||
|
||||
// TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more
|
||||
// elements for v3s16
|
||||
@ -296,7 +297,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
|
||||
getActionDefinitionsBuilder({G_UADDO, G_USUBO,
|
||||
G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
|
||||
.legalFor({{S32, S1}})
|
||||
.legalFor({{S32, S1}, {S32, S32}})
|
||||
.clampScalar(0, S32, S32)
|
||||
.scalarize(0); // TODO: Implement.
|
||||
|
||||
@ -505,9 +506,20 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
|
||||
auto &CmpBuilder =
|
||||
getActionDefinitionsBuilder(G_ICMP)
|
||||
// The compare output type differs based on the register bank of the output,
|
||||
// so make both s1 and s32 legal.
|
||||
//
|
||||
// Scalar compares producing output in scc will be promoted to s32, as that
|
||||
// is the allocatable register type that will be needed for the copy from
|
||||
// scc. This will be promoted during RegBankSelect, and we assume something
|
||||
// before that won't try to use s32 result types.
|
||||
//
|
||||
// Vector compares producing an output in vcc/SGPR will use s1 in VCC reg
|
||||
// bank.
|
||||
.legalForCartesianProduct(
|
||||
{S1}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr})
|
||||
.legalFor({{S1, S32}, {S1, S64}});
|
||||
.legalForCartesianProduct(
|
||||
{S32}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr});
|
||||
if (ST.has16BitInsts()) {
|
||||
CmpBuilder.legalFor({{S1, S16}});
|
||||
}
|
||||
@ -516,7 +528,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
.widenScalarToNextPow2(1)
|
||||
.clampScalar(1, S32, S64)
|
||||
.scalarize(0)
|
||||
.legalIf(all(typeIs(0, S1), isPointer(1)));
|
||||
.legalIf(all(typeInSet(0, {S1, S32}), isPointer(1)));
|
||||
|
||||
getActionDefinitionsBuilder(G_FCMP)
|
||||
.legalForCartesianProduct({S1}, ST.has16BitInsts() ? FPTypes16 : FPTypesBase)
|
||||
@ -888,10 +900,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
.lower();
|
||||
|
||||
// TODO: Pointer types, any 32-bit or 64-bit vector
|
||||
|
||||
// Condition should be s32 for scalar, s1 for vector.
|
||||
getActionDefinitionsBuilder(G_SELECT)
|
||||
.legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16,
|
||||
GlobalPtr, LocalPtr, FlatPtr, PrivatePtr,
|
||||
LLT::vector(2, LocalPtr), LLT::vector(2, PrivatePtr)}, {S1})
|
||||
LLT::vector(2, LocalPtr), LLT::vector(2, PrivatePtr)}, {S1, S32})
|
||||
.clampScalar(0, S16, S64)
|
||||
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
|
||||
.fewerElementsIf(numElementsNotEven(0), scalarize(0))
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
|
||||
#include "SIMachineFunctionInfo.h"
|
||||
#include "SIRegisterInfo.h"
|
||||
#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
|
||||
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
|
||||
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
|
||||
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
|
||||
@ -40,13 +41,15 @@ namespace {
|
||||
// Observer to apply a register bank to new registers created by LegalizerHelper.
|
||||
class ApplyRegBankMapping final : public GISelChangeObserver {
|
||||
private:
|
||||
const AMDGPURegisterBankInfo &RBI;
|
||||
MachineRegisterInfo &MRI;
|
||||
const RegisterBank *NewBank;
|
||||
SmallVector<MachineInstr *, 4> NewInsts;
|
||||
|
||||
public:
|
||||
ApplyRegBankMapping(MachineRegisterInfo &MRI_, const RegisterBank *RB)
|
||||
: MRI(MRI_), NewBank(RB) {}
|
||||
ApplyRegBankMapping(const AMDGPURegisterBankInfo &RBI_,
|
||||
MachineRegisterInfo &MRI_, const RegisterBank *RB)
|
||||
: RBI(RBI_), MRI(MRI_), NewBank(RB) {}
|
||||
|
||||
~ApplyRegBankMapping() {
|
||||
for (MachineInstr *MI : NewInsts)
|
||||
@ -55,6 +58,46 @@ public:
|
||||
|
||||
/// Set any registers that don't have a set register class or bank to SALU.
|
||||
void applyBank(MachineInstr &MI) {
|
||||
const unsigned Opc = MI.getOpcode();
|
||||
if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT ||
|
||||
Opc == AMDGPU::G_SEXT) {
|
||||
// LegalizerHelper wants to use the basic legalization artifacts when
|
||||
// widening etc. We don't handle selection with vcc in artifact sources,
|
||||
// so we need to use a sslect instead to handle these properly.
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
Register SrcReg = MI.getOperand(1).getReg();
|
||||
const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);
|
||||
if (SrcBank == &AMDGPU::VCCRegBank) {
|
||||
const LLT S1 = LLT::scalar(1);
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
assert(MRI.getType(SrcReg) == S1);
|
||||
assert(MRI.getType(DstReg) == S32);
|
||||
assert(NewBank == &AMDGPU::VGPRRegBank);
|
||||
|
||||
// Replace the extension with a select, which really uses the boolean
|
||||
// source.
|
||||
MachineIRBuilder B(MI);
|
||||
auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
|
||||
auto False = B.buildConstant(S32, 0);
|
||||
B.buildSelect(DstReg, SrcReg, True, False);
|
||||
MRI.setRegBank(True.getReg(0), *NewBank);
|
||||
MRI.setRegBank(False.getReg(0), *NewBank);
|
||||
MI.eraseFromParent();
|
||||
}
|
||||
|
||||
assert(!MRI.getRegClassOrRegBank(DstReg));
|
||||
MRI.setRegBank(DstReg, *NewBank);
|
||||
return;
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
if (Opc == AMDGPU::G_TRUNC) {
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);
|
||||
assert(DstBank != &AMDGPU::VCCRegBank);
|
||||
}
|
||||
#endif
|
||||
|
||||
for (MachineOperand &Op : MI.operands()) {
|
||||
if (!Op.isReg())
|
||||
continue;
|
||||
@ -64,10 +107,14 @@ public:
|
||||
continue;
|
||||
|
||||
const RegisterBank *RB = NewBank;
|
||||
// FIXME: This might not be enough to detect when SCC should be used.
|
||||
if (MRI.getType(Reg) == LLT::scalar(1))
|
||||
RB = (NewBank == &AMDGPU::SGPRRegBank ?
|
||||
&AMDGPU::SCCRegBank : &AMDGPU::VCCRegBank);
|
||||
if (MRI.getType(Reg) == LLT::scalar(1)) {
|
||||
assert(NewBank == &AMDGPU::VGPRRegBank &&
|
||||
"s1 operands should only be used for vector bools");
|
||||
assert((MI.getOpcode() != AMDGPU::G_TRUNC &&
|
||||
MI.getOpcode() != AMDGPU::G_ANYEXT) &&
|
||||
"not expecting legalization artifacts here");
|
||||
RB = &AMDGPU::VCCRegBank;
|
||||
}
|
||||
|
||||
MRI.setRegBank(Reg, *RB);
|
||||
}
|
||||
@ -133,15 +180,13 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
|
||||
// have been a truncate from an arbitrary value, in which case a copy (lowered
|
||||
// as a compare with 0) needs to be inserted.
|
||||
if (Size == 1 &&
|
||||
(Dst.getID() == AMDGPU::SCCRegBankID ||
|
||||
Dst.getID() == AMDGPU::SGPRRegBankID) &&
|
||||
(Dst.getID() == AMDGPU::SGPRRegBankID) &&
|
||||
(isVectorRegisterBank(Src) ||
|
||||
Src.getID() == AMDGPU::SGPRRegBankID ||
|
||||
Src.getID() == AMDGPU::VCCRegBankID))
|
||||
return std::numeric_limits<unsigned>::max();
|
||||
|
||||
if (Dst.getID() == AMDGPU::SCCRegBankID &&
|
||||
Src.getID() == AMDGPU::VCCRegBankID)
|
||||
if (Src.getID() == AMDGPU::VCCRegBankID)
|
||||
return std::numeric_limits<unsigned>::max();
|
||||
|
||||
// There is no direct copy between AGPRs.
|
||||
@ -183,12 +228,19 @@ AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
|
||||
if (&RC == &AMDGPU::SReg_1RegClass)
|
||||
return AMDGPU::VCCRegBank;
|
||||
|
||||
if (TRI->isSGPRClass(&RC))
|
||||
return AMDGPU::SGPRRegBank;
|
||||
if (TRI->isAGPRClass(&RC))
|
||||
return AMDGPU::AGPRRegBank;
|
||||
// We promote real scalar booleans to SReg_32. Any SGPR using s1 is really a
|
||||
// VCC-like use.
|
||||
if (TRI->isSGPRClass(&RC)) {
|
||||
// FIXME: This probably came from a copy from a physical register, which
|
||||
// should be inferrrable from the copied to-type. We don't have many boolean
|
||||
// physical register constraints so just assume a normal SGPR for now.
|
||||
if (!Ty.isValid())
|
||||
return AMDGPU::SGPRRegBank;
|
||||
|
||||
return AMDGPU::VGPRRegBank;
|
||||
return Ty == LLT::scalar(1) ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank;
|
||||
}
|
||||
|
||||
return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank;
|
||||
}
|
||||
|
||||
template <unsigned NumOps>
|
||||
@ -383,11 +435,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
case TargetOpcode::G_CONSTANT: {
|
||||
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
||||
if (Size == 1) {
|
||||
static const OpRegBankEntry<1> Table[4] = {
|
||||
static const OpRegBankEntry<1> Table[3] = {
|
||||
{ { AMDGPU::VGPRRegBankID }, 1 },
|
||||
{ { AMDGPU::SGPRRegBankID }, 1 },
|
||||
{ { AMDGPU::VCCRegBankID }, 1 },
|
||||
{ { AMDGPU::SCCRegBankID }, 1 }
|
||||
{ { AMDGPU::VCCRegBankID }, 1 }
|
||||
};
|
||||
|
||||
return addMappingFromTable<1>(MI, MRI, {{ 0 }}, Table);
|
||||
@ -414,25 +465,17 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
// s_{and|or|xor}_b32 set scc when the result of the 32-bit op is not 0.
|
||||
const InstructionMapping &SCCMapping = getInstructionMapping(
|
||||
1, 1, getOperandsMapping(
|
||||
{AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
|
||||
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32)}),
|
||||
3); // Num Operands
|
||||
AltMappings.push_back(&SCCMapping);
|
||||
|
||||
const InstructionMapping &SGPRMapping = getInstructionMapping(
|
||||
1, 1, getOperandsMapping(
|
||||
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
|
||||
3); // Num Operands
|
||||
AltMappings.push_back(&SGPRMapping);
|
||||
|
||||
const InstructionMapping &VCCMapping0 = getInstructionMapping(
|
||||
2, 10, getOperandsMapping(
|
||||
2, 1, getOperandsMapping(
|
||||
{AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size)}),
|
||||
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size)}),
|
||||
3); // Num Operands
|
||||
AltMappings.push_back(&VCCMapping0);
|
||||
return AltMappings;
|
||||
@ -513,9 +556,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
|
||||
}
|
||||
case TargetOpcode::G_ICMP: {
|
||||
// TODO: Should report 32-bit for scalar output type.
|
||||
unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
|
||||
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
|
||||
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
|
||||
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
|
||||
nullptr, // Predicate operand.
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
|
||||
@ -552,7 +596,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
|
||||
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
|
||||
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
|
||||
4); // Num Operands
|
||||
@ -593,10 +637,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
|
||||
getOperandsMapping(
|
||||
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
|
||||
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),
|
||||
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}),
|
||||
5); // Num Operands
|
||||
AltMappings.push_back(&SSMapping);
|
||||
|
||||
@ -613,9 +657,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
|
||||
case AMDGPU::G_BRCOND: {
|
||||
assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
|
||||
|
||||
// TODO: Change type to 32 for scalar
|
||||
const InstructionMapping &SMapping = getInstructionMapping(
|
||||
1, 1, getOperandsMapping(
|
||||
{AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1), nullptr}),
|
||||
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), nullptr}),
|
||||
2); // Num Operands
|
||||
AltMappings.push_back(&SMapping);
|
||||
|
||||
@ -1112,7 +1157,7 @@ bool AMDGPURegisterBankInfo::applyMappingWideLoad(MachineInstr &MI,
|
||||
unsigned SplitElts =
|
||||
MaxNonSmrdLoadSize / LoadTy.getScalarType().getSizeInBits();
|
||||
const LLT LoadSplitTy = LLT::vector(SplitElts, LoadTy.getScalarType());
|
||||
ApplyRegBankMapping O(MRI, &AMDGPU::VGPRRegBank);
|
||||
ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank);
|
||||
GISelObserverWrapper Observer(&O);
|
||||
B.setChangeObserver(Observer);
|
||||
LegalizerHelper Helper(B.getMF(), Observer, B);
|
||||
@ -1171,6 +1216,39 @@ bool AMDGPURegisterBankInfo::applyMappingImage(
|
||||
return true;
|
||||
}
|
||||
|
||||
// FIXME: Duplicated from LegalizerHelper
|
||||
static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
|
||||
switch (Opc) {
|
||||
case TargetOpcode::G_SMIN:
|
||||
return CmpInst::ICMP_SLT;
|
||||
case TargetOpcode::G_SMAX:
|
||||
return CmpInst::ICMP_SGT;
|
||||
case TargetOpcode::G_UMIN:
|
||||
return CmpInst::ICMP_ULT;
|
||||
case TargetOpcode::G_UMAX:
|
||||
return CmpInst::ICMP_UGT;
|
||||
default:
|
||||
llvm_unreachable("not in integer min/max");
|
||||
}
|
||||
}
|
||||
|
||||
// FIXME: Duplicated from LegalizerHelper, except changing the boolean type.
|
||||
void AMDGPURegisterBankInfo::lowerScalarMinMax(MachineIRBuilder &B,
|
||||
MachineInstr &MI) const {
|
||||
Register Dst = MI.getOperand(0).getReg();
|
||||
Register Src0 = MI.getOperand(1).getReg();
|
||||
Register Src1 = MI.getOperand(2).getReg();
|
||||
|
||||
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
|
||||
LLT CmpType = LLT::scalar(32);
|
||||
|
||||
auto Cmp = B.buildICmp(Pred, CmpType, Src0, Src1);
|
||||
B.buildSelect(Dst, Cmp, Src0, Src1);
|
||||
|
||||
B.getMRI()->setRegBank(Cmp.getReg(0), AMDGPU::SGPRRegBank);
|
||||
MI.eraseFromParent();
|
||||
}
|
||||
|
||||
// For cases where only a single copy is inserted for matching register banks.
|
||||
// Replace the register in the instruction operand
|
||||
static void substituteSimpleCopyRegs(
|
||||
@ -1366,16 +1444,122 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
unsigned Opc = MI.getOpcode();
|
||||
MachineRegisterInfo &MRI = OpdMapper.getMRI();
|
||||
switch (Opc) {
|
||||
case AMDGPU::G_PHI: {
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
LLT DstTy = MRI.getType(DstReg);
|
||||
if (DstTy != LLT::scalar(1))
|
||||
break;
|
||||
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
const RegisterBank *DstBank =
|
||||
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
|
||||
if (DstBank == &AMDGPU::VCCRegBank) {
|
||||
applyDefaultMapping(OpdMapper);
|
||||
// The standard handling only considers the result register bank for
|
||||
// phis. For VCC, blindly inserting a copy when the phi is lowered will
|
||||
// produce an invalid copy. We can only copy with some kind of compare to
|
||||
// get a vector boolean result. Insert a regitser bank copy that will be
|
||||
// correctly lowered to a compare.
|
||||
MachineIRBuilder B(*MI.getParent()->getParent());
|
||||
|
||||
for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
|
||||
Register SrcReg = MI.getOperand(I).getReg();
|
||||
const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
|
||||
|
||||
if (SrcBank != &AMDGPU::VCCRegBank) {
|
||||
MachineBasicBlock *SrcMBB = MI.getOperand(I + 1).getMBB();
|
||||
B.setInsertPt(*SrcMBB, SrcMBB->getFirstTerminator());
|
||||
|
||||
auto Copy = B.buildCopy(LLT::scalar(1), SrcReg);
|
||||
MRI.setRegBank(Copy.getReg(0), AMDGPU::VCCRegBank);
|
||||
MI.getOperand(I).setReg(Copy.getReg(0));
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
// Phi handling is strange and only considers the bank of the destination.
|
||||
substituteSimpleCopyRegs(OpdMapper, 0);
|
||||
|
||||
// Promote SGPR/VGPR booleans to s32
|
||||
MachineFunction *MF = MI.getParent()->getParent();
|
||||
ApplyRegBankMapping ApplyBank(*this, MRI, DstBank);
|
||||
GISelObserverWrapper Observer(&ApplyBank);
|
||||
MachineIRBuilder B(MI);
|
||||
LegalizerHelper Helper(*MF, Observer, B);
|
||||
|
||||
if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
|
||||
llvm_unreachable("widen scalar should have succeeded");
|
||||
|
||||
return;
|
||||
}
|
||||
case AMDGPU::G_ICMP:
|
||||
case AMDGPU::G_UADDO:
|
||||
case AMDGPU::G_USUBO:
|
||||
case AMDGPU::G_UADDE:
|
||||
case AMDGPU::G_SADDE:
|
||||
case AMDGPU::G_USUBE:
|
||||
case AMDGPU::G_SSUBE: {
|
||||
unsigned BoolDstOp = Opc == AMDGPU::G_ICMP ? 0 : 1;
|
||||
Register DstReg = MI.getOperand(BoolDstOp).getReg();
|
||||
|
||||
const RegisterBank *DstBank =
|
||||
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
|
||||
if (DstBank != &AMDGPU::SGPRRegBank)
|
||||
break;
|
||||
|
||||
const bool HasCarryIn = MI.getNumOperands() == 5;
|
||||
|
||||
// If this is a scalar compare, promote the result to s32, as the selection
|
||||
// will end up using a copy to a 32-bit vreg.
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
Register NewDstReg = MRI.createGenericVirtualRegister(S32);
|
||||
MRI.setRegBank(NewDstReg, AMDGPU::SGPRRegBank);
|
||||
MI.getOperand(BoolDstOp).setReg(NewDstReg);
|
||||
MachineIRBuilder B(MI);
|
||||
|
||||
if (HasCarryIn) {
|
||||
Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
|
||||
MRI.setRegBank(NewSrcReg, AMDGPU::SGPRRegBank);
|
||||
B.buildZExt(NewSrcReg, MI.getOperand(4).getReg());
|
||||
MI.getOperand(4).setReg(NewSrcReg);
|
||||
}
|
||||
|
||||
MachineBasicBlock *MBB = MI.getParent();
|
||||
B.setInsertPt(*MBB, std::next(MI.getIterator()));
|
||||
B.buildTrunc(DstReg, NewDstReg);
|
||||
return;
|
||||
}
|
||||
case AMDGPU::G_SELECT: {
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
LLT DstTy = MRI.getType(DstReg);
|
||||
|
||||
SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));
|
||||
if (CondRegs.empty())
|
||||
CondRegs.push_back(MI.getOperand(1).getReg());
|
||||
else {
|
||||
assert(CondRegs.size() == 1);
|
||||
}
|
||||
|
||||
const RegisterBank *CondBank = getRegBank(CondRegs[0], MRI, *TRI);
|
||||
if (CondBank == &AMDGPU::SGPRRegBank) {
|
||||
MachineIRBuilder B(MI);
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
Register NewCondReg = MRI.createGenericVirtualRegister(S32);
|
||||
MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank);
|
||||
|
||||
MI.getOperand(1).setReg(NewCondReg);
|
||||
B.buildZExt(NewCondReg, CondRegs[0]);
|
||||
}
|
||||
|
||||
if (DstTy.getSizeInBits() != 64)
|
||||
break;
|
||||
|
||||
MachineIRBuilder B(MI);
|
||||
LLT HalfTy = getHalfSizedType(DstTy);
|
||||
|
||||
SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
|
||||
SmallVector<Register, 1> Src0Regs(OpdMapper.getVRegs(1));
|
||||
SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
|
||||
SmallVector<Register, 2> Src2Regs(OpdMapper.getVRegs(3));
|
||||
|
||||
@ -1385,13 +1569,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
break;
|
||||
}
|
||||
|
||||
MachineIRBuilder B(MI);
|
||||
if (Src0Regs.empty())
|
||||
Src0Regs.push_back(MI.getOperand(1).getReg());
|
||||
else {
|
||||
assert(Src0Regs.size() == 1);
|
||||
}
|
||||
|
||||
if (Src1Regs.empty())
|
||||
split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
|
||||
else {
|
||||
@ -1405,13 +1582,32 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
|
||||
setRegsToType(MRI, DefRegs, HalfTy);
|
||||
|
||||
B.buildSelect(DefRegs[0], Src0Regs[0], Src1Regs[0], Src2Regs[0]);
|
||||
B.buildSelect(DefRegs[1], Src0Regs[0], Src1Regs[1], Src2Regs[1]);
|
||||
B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]);
|
||||
B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]);
|
||||
|
||||
MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
}
|
||||
case AMDGPU::G_BRCOND: {
|
||||
Register CondReg = MI.getOperand(0).getReg();
|
||||
// FIXME: Should use legalizer helper, but should change bool ext type.
|
||||
const RegisterBank *CondBank =
|
||||
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
|
||||
|
||||
if (CondBank == &AMDGPU::SGPRRegBank) {
|
||||
MachineIRBuilder B(MI);
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
Register NewCondReg = MRI.createGenericVirtualRegister(S32);
|
||||
MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank);
|
||||
|
||||
MI.getOperand(0).setReg(NewCondReg);
|
||||
B.buildZExt(NewCondReg, CondReg);
|
||||
return;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case AMDGPU::G_AND:
|
||||
case AMDGPU::G_OR:
|
||||
case AMDGPU::G_XOR: {
|
||||
@ -1419,6 +1615,25 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
// there is a VGPR input.
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
LLT DstTy = MRI.getType(DstReg);
|
||||
|
||||
if (DstTy.getSizeInBits() == 1) {
|
||||
const RegisterBank *DstBank =
|
||||
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
|
||||
if (DstBank == &AMDGPU::VCCRegBank)
|
||||
break;
|
||||
|
||||
MachineFunction *MF = MI.getParent()->getParent();
|
||||
ApplyRegBankMapping ApplyBank(*this, MRI, DstBank);
|
||||
GISelObserverWrapper Observer(&ApplyBank);
|
||||
MachineIRBuilder B(MI);
|
||||
LegalizerHelper Helper(*MF, Observer, B);
|
||||
|
||||
if (Helper.widenScalar(MI, 0, LLT::scalar(32)) !=
|
||||
LegalizerHelper::Legalized)
|
||||
llvm_unreachable("widen scalar should have succeeded");
|
||||
return;
|
||||
}
|
||||
|
||||
if (DstTy.getSizeInBits() != 64)
|
||||
break;
|
||||
|
||||
@ -1484,7 +1699,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
// 16-bit operations are VALU only, but can be promoted to 32-bit SALU.
|
||||
MachineFunction *MF = MI.getParent()->getParent();
|
||||
MachineIRBuilder B(MI);
|
||||
ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
|
||||
ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank);
|
||||
GISelObserverWrapper Observer(&ApplySALU);
|
||||
LegalizerHelper Helper(*MF, Observer, B);
|
||||
|
||||
@ -1505,9 +1720,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
|
||||
MachineFunction *MF = MI.getParent()->getParent();
|
||||
MachineIRBuilder B(MI);
|
||||
ApplyRegBankMapping ApplySALU(MRI, &AMDGPU::SGPRRegBank);
|
||||
GISelObserverWrapper Observer(&ApplySALU);
|
||||
LegalizerHelper Helper(*MF, Observer, B);
|
||||
|
||||
// Turn scalar min/max into a compare and select.
|
||||
LLT Ty = MRI.getType(DstReg);
|
||||
@ -1515,17 +1727,18 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
LLT S16 = LLT::scalar(16);
|
||||
|
||||
if (Ty == S16) {
|
||||
ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank);
|
||||
GISelObserverWrapper Observer(&ApplySALU);
|
||||
LegalizerHelper Helper(*MF, Observer, B);
|
||||
|
||||
// Need to widen to s32, and expand as cmp + select.
|
||||
if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
|
||||
llvm_unreachable("widenScalar should have succeeded");
|
||||
|
||||
// FIXME: This is relying on widenScalar leaving MI in place.
|
||||
if (Helper.lower(MI, 0, S32) != LegalizerHelper::Legalized)
|
||||
llvm_unreachable("lower should have succeeded");
|
||||
} else {
|
||||
if (Helper.lower(MI, 0, Ty) != LegalizerHelper::Legalized)
|
||||
llvm_unreachable("lower should have succeeded");
|
||||
}
|
||||
lowerScalarMinMax(B, MI);
|
||||
} else
|
||||
lowerScalarMinMax(B, MI);
|
||||
|
||||
return;
|
||||
}
|
||||
@ -1543,7 +1756,6 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
LLT DstTy = MRI.getType(DstReg);
|
||||
if (DstTy.isScalar() &&
|
||||
SrcBank != &AMDGPU::SGPRRegBank &&
|
||||
SrcBank != &AMDGPU::SCCRegBank &&
|
||||
SrcBank != &AMDGPU::VCCRegBank &&
|
||||
// FIXME: Should handle any type that round to s64 when irregular
|
||||
// breakdowns supported.
|
||||
@ -1574,16 +1786,15 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
if (SrcTy != LLT::scalar(1))
|
||||
return;
|
||||
|
||||
if (SrcBank == &AMDGPU::SCCRegBank || SrcBank == &AMDGPU::VCCRegBank) {
|
||||
if (SrcBank == &AMDGPU::VCCRegBank) {
|
||||
SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
|
||||
|
||||
const RegisterBank *DstBank = SrcBank == &AMDGPU::SCCRegBank ?
|
||||
&AMDGPU::SGPRRegBank : &AMDGPU::VGPRRegBank;
|
||||
const RegisterBank *DstBank = &AMDGPU::VGPRRegBank;
|
||||
|
||||
unsigned DstSize = DstTy.getSizeInBits();
|
||||
// 64-bit select is SGPR only
|
||||
const bool UseSel64 = DstSize > 32 &&
|
||||
SrcBank->getID() == AMDGPU::SCCRegBankID;
|
||||
SrcBank->getID() == AMDGPU::SGPRRegBankID;
|
||||
|
||||
// TODO: Should s16 select be legal?
|
||||
LLT SelType = UseSel64 ? LLT::scalar(64) : LLT::scalar(32);
|
||||
@ -1594,7 +1805,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
|
||||
MRI.setRegBank(False.getReg(0), *DstBank);
|
||||
MRI.setRegBank(DstReg, *DstBank);
|
||||
|
||||
if (DstSize > 32 && SrcBank->getID() != AMDGPU::SCCRegBankID) {
|
||||
if (DstSize > 32) {
|
||||
B.buildSelect(DefRegs[0], SrcReg, True, False);
|
||||
B.buildCopy(DefRegs[1], DefRegs[0]);
|
||||
} else if (DstSize < 32) {
|
||||
@ -1955,11 +2166,8 @@ bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
|
||||
continue;
|
||||
Register Reg = MI.getOperand(i).getReg();
|
||||
if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
|
||||
if (isVectorRegisterBank(*Bank))
|
||||
if (Bank->getID() != AMDGPU::SGPRRegBankID)
|
||||
return false;
|
||||
|
||||
assert(Bank->getID() == AMDGPU::SGPRRegBankID ||
|
||||
Bank->getID() == AMDGPU::SCCRegBankID);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
@ -1973,8 +2181,7 @@ AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
|
||||
|
||||
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
||||
unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
|
||||
unsigned BankID = Size == 1 ? AMDGPU::SCCRegBankID : AMDGPU::SGPRRegBankID;
|
||||
OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
|
||||
OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
|
||||
}
|
||||
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
|
||||
MI.getNumOperands());
|
||||
@ -2228,10 +2435,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
break;
|
||||
}
|
||||
|
||||
// FIXME: Need to promote SGPR case to s32
|
||||
unsigned OpBank = Bank->getID();
|
||||
if (OpBank == AMDGPU::SCCRegBankID)
|
||||
OpBank = AMDGPU::SGPRRegBankID;
|
||||
|
||||
ResultBank = regBankBoolUnion(ResultBank, OpBank);
|
||||
}
|
||||
|
||||
@ -2273,10 +2478,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
TargetBankID = AMDGPU::VCCRegBankID;
|
||||
BankLHS = AMDGPU::VCCRegBankID;
|
||||
BankRHS = AMDGPU::VCCRegBankID;
|
||||
} else if (DstBank == &AMDGPU::SCCRegBank) {
|
||||
TargetBankID = AMDGPU::SCCRegBankID;
|
||||
BankLHS = AMDGPU::SGPRRegBankID;
|
||||
BankRHS = AMDGPU::SGPRRegBankID;
|
||||
} else {
|
||||
BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
|
||||
AMDGPU::SGPRRegBankID);
|
||||
@ -2298,13 +2499,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
BankRHS = AMDGPU::VCCRegBankID;
|
||||
} else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) {
|
||||
TargetBankID = AMDGPU::SGPRRegBankID;
|
||||
} else if (BankLHS == AMDGPU::SCCRegBankID || BankRHS == AMDGPU::SCCRegBankID) {
|
||||
// The operation must be done on a 32-bit register, but it will set
|
||||
// scc. The result type could interchangably be SCC or SGPR, since
|
||||
// both values will be produced.
|
||||
TargetBankID = AMDGPU::SCCRegBankID;
|
||||
BankLHS = AMDGPU::SGPRRegBankID;
|
||||
BankRHS = AMDGPU::SGPRRegBankID;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2480,7 +2674,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
unsigned Bank = getRegBankID(Src, MRI, *TRI);
|
||||
unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
|
||||
unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
|
||||
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
|
||||
OpdsMapping[0] = DstSize == 1 && Bank != AMDGPU::SGPRRegBankID ?
|
||||
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize) :
|
||||
AMDGPU::getValueMapping(Bank, DstSize);
|
||||
OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
|
||||
break;
|
||||
}
|
||||
@ -2496,7 +2692,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
const RegisterBank *SrcBank = getRegBank(Src, MRI, *TRI);
|
||||
assert(SrcBank);
|
||||
switch (SrcBank->getID()) {
|
||||
case AMDGPU::SCCRegBankID:
|
||||
case AMDGPU::SGPRRegBankID:
|
||||
DstBank = AMDGPU::SGPRRegBankID;
|
||||
break;
|
||||
@ -2557,9 +2752,13 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
(Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) &&
|
||||
Subtarget.hasScalarCompareEq64()));
|
||||
|
||||
unsigned Op0Bank = CanUseSCC ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
|
||||
unsigned Op0Bank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;
|
||||
|
||||
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
|
||||
// TODO: Use 32-bit for scalar output size.
|
||||
// SCC results will need to be copied to a 32-bit SGPR virtual register.
|
||||
const unsigned ResultSize = 1;
|
||||
|
||||
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, ResultSize);
|
||||
OpdsMapping[1] = nullptr; // Predicate Operand.
|
||||
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
|
||||
OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
|
||||
@ -3010,19 +3209,20 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
Op3Bank == AMDGPU::SGPRRegBankID;
|
||||
|
||||
unsigned CondBankDefault = SGPRSrcs ?
|
||||
AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
|
||||
AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;
|
||||
unsigned CondBank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
|
||||
CondBankDefault);
|
||||
if (CondBank == AMDGPU::SGPRRegBankID)
|
||||
CondBank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
|
||||
CondBank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;
|
||||
else if (CondBank == AMDGPU::VGPRRegBankID)
|
||||
CondBank = AMDGPU::VCCRegBankID;
|
||||
|
||||
unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SCCRegBankID ?
|
||||
unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SGPRRegBankID ?
|
||||
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
|
||||
|
||||
assert(CondBank == AMDGPU::VCCRegBankID || CondBank == AMDGPU::SCCRegBankID);
|
||||
assert(CondBank == AMDGPU::VCCRegBankID || CondBank == AMDGPU::SGPRRegBankID);
|
||||
|
||||
// TODO: Should report 32-bit for scalar condition type.
|
||||
if (Size == 64) {
|
||||
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
|
||||
OpdsMapping[1] = AMDGPU::getValueMapping(CondBank, 1);
|
||||
@ -3062,7 +3262,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
|
||||
AMDGPU::SGPRRegBankID);
|
||||
assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
|
||||
if (Bank != AMDGPU::SCCRegBankID)
|
||||
if (Bank != AMDGPU::SGPRRegBankID)
|
||||
Bank = AMDGPU::VCCRegBankID;
|
||||
|
||||
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1);
|
||||
|
||||
@ -40,10 +40,12 @@ protected:
|
||||
#include "AMDGPUGenRegisterBank.inc"
|
||||
};
|
||||
class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
|
||||
public:
|
||||
const GCNSubtarget &Subtarget;
|
||||
const SIRegisterInfo *TRI;
|
||||
const SIInstrInfo *TII;
|
||||
|
||||
private:
|
||||
bool collectWaterfallOperands(
|
||||
SmallSet<Register, 4> &SGPROperandRegs,
|
||||
MachineInstr &MI,
|
||||
@ -74,6 +76,8 @@ class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
|
||||
const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
|
||||
MachineRegisterInfo &MRI, int RSrcIdx) const;
|
||||
|
||||
void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
|
||||
|
||||
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
|
||||
Register Reg) const;
|
||||
|
||||
|
||||
@ -14,8 +14,6 @@ def VGPRRegBank : RegisterBank<"VGPR",
|
||||
[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512, VReg_1024]
|
||||
>;
|
||||
|
||||
def SCCRegBank : RegisterBank <"SCC", [SReg_32, SCC_CLASS]>;
|
||||
|
||||
// It is helpful to distinguish conditions from ordinary SGPRs.
|
||||
def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
|
||||
|
||||
|
||||
@ -1775,14 +1775,6 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
|
||||
&AMDGPU::SReg_32_XM0_XEXECRegClass : &AMDGPU::SReg_64_XEXECRegClass;
|
||||
case AMDGPU::SGPRRegBankID:
|
||||
return &AMDGPU::SReg_32RegClass;
|
||||
case AMDGPU::SCCRegBankID:
|
||||
// This needs to return an allocatable class, so don't bother returning
|
||||
// the dummy SCC class.
|
||||
//
|
||||
// FIXME: This is a grotesque hack. We use SGPR_32 as an indication this
|
||||
// was not an VCC bank value since we use the larger class SReg_32 for
|
||||
// other values. These should all use SReg_32.
|
||||
return &AMDGPU::SGPR_32RegClass;
|
||||
default:
|
||||
llvm_unreachable("unknown register bank");
|
||||
}
|
||||
|
||||
105
test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
Normal file
105
test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
Normal file
@ -0,0 +1,105 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
; End to end tests for scalar vs. vector boolean legalization strategies.
|
||||
|
||||
define amdgpu_ps float @select_vgpr_sgpr_trunc_cond(i32 inreg %a, i32 %b, i32 %c) {
|
||||
; GCN-LABEL: select_vgpr_sgpr_trunc_cond:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_and_b32 s0, 1, s0
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%cc = trunc i32 %a to i1
|
||||
%r = select i1 %cc, i32 %b, i32 %c
|
||||
%r.f = bitcast i32 %r to float
|
||||
ret float %r.f
|
||||
}
|
||||
|
||||
define amdgpu_ps float @select_vgpr_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 %b, i32 %c) {
|
||||
; GCN-LABEL: select_vgpr_sgpr_trunc_and_cond:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_and_b32 s0, s0, s1
|
||||
; GCN-NEXT: s_and_b32 s0, 1, s0
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%cc.0 = trunc i32 %a.0 to i1
|
||||
%cc.1 = trunc i32 %a.1 to i1
|
||||
%and = and i1 %cc.0, %cc.1
|
||||
%r = select i1 %and, i32 %b, i32 %c
|
||||
%r.f = bitcast i32 %r to float
|
||||
ret float %r.f
|
||||
}
|
||||
|
||||
define amdgpu_ps i32 @select_sgpr_trunc_and_cond(i32 inreg %a.0, i32 inreg %a.1, i32 inreg %b, i32 inreg %c) {
|
||||
; GCN-LABEL: select_sgpr_trunc_and_cond:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_and_b32 s0, s0, s1
|
||||
; GCN-NEXT: s_and_b32 s0, s0, 1
|
||||
; GCN-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GCN-NEXT: s_cselect_b32 s0, s2, s3
|
||||
; GCN-NEXT: ; return to shader part epilog
|
||||
%cc.0 = trunc i32 %a.0 to i1
|
||||
%cc.1 = trunc i32 %a.1 to i1
|
||||
%and = and i1 %cc.0, %cc.1
|
||||
%r = select i1 %and, i32 %b, i32 %c
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sgpr_trunc_brcond(i32 %cond) {
|
||||
; GCN-LABEL: sgpr_trunc_brcond:
|
||||
; GCN: ; %bb.0: ; %entry
|
||||
; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_and_b32 s0, s0, 1
|
||||
; GCN-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GCN-NEXT: s_cbranch_scc0 BB3_2
|
||||
; GCN-NEXT: ; %bb.1: ; %bb0
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: flat_store_dword v[0:1], v0
|
||||
; GCN-NEXT: BB3_2: ; %bb1
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 1
|
||||
; GCN-NEXT: flat_store_dword v[0:1], v0
|
||||
entry:
|
||||
%trunc = trunc i32 %cond to i1
|
||||
br i1 %trunc, label %bb0, label %bb1
|
||||
|
||||
bb0:
|
||||
store volatile i32 0, i32 addrspace(1)* undef
|
||||
unreachable
|
||||
|
||||
bb1:
|
||||
store volatile i32 1, i32 addrspace(1)* undef
|
||||
unreachable
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @brcond_sgpr_trunc_and(i32 %cond0, i32 %cond1) {
|
||||
; GCN-LABEL: brcond_sgpr_trunc_and:
|
||||
; GCN: ; %bb.0: ; %entry
|
||||
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_and_b32 s0, s0, s1
|
||||
; GCN-NEXT: s_and_b32 s0, s0, 1
|
||||
; GCN-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GCN-NEXT: s_cbranch_scc0 BB4_2
|
||||
; GCN-NEXT: ; %bb.1: ; %bb0
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: flat_store_dword v[0:1], v0
|
||||
; GCN-NEXT: BB4_2: ; %bb1
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 1
|
||||
; GCN-NEXT: flat_store_dword v[0:1], v0
|
||||
entry:
|
||||
%trunc0 = trunc i32 %cond0 to i1
|
||||
%trunc1 = trunc i32 %cond1 to i1
|
||||
%and = and i1 %trunc0, %trunc1
|
||||
br i1 %and, label %bb0, label %bb1
|
||||
|
||||
bb0:
|
||||
store volatile i32 0, i32 addrspace(1)* undef
|
||||
unreachable
|
||||
|
||||
bb1:
|
||||
store volatile i32 1, i32 addrspace(1)* undef
|
||||
unreachable
|
||||
}
|
||||
@ -41,6 +41,7 @@ body: |
|
||||
S_ENDPGM 0, implicit %5
|
||||
...
|
||||
|
||||
# Should fail to select
|
||||
---
|
||||
|
||||
name: and_s1_sgpr_sgpr_sgpr
|
||||
@ -74,40 +75,6 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: and_s1_scc_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; WAVE64-LABEL: name: and_s1_scc_sgpr_sgpr
|
||||
; WAVE64: liveins: $sgpr0, $sgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE64: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[AND]](s1)
|
||||
; WAVE32-LABEL: name: and_s1_scc_sgpr_sgpr
|
||||
; WAVE32: liveins: $sgpr0, $sgpr1
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE32: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[AND]](s1)
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s1) = G_TRUNC %0
|
||||
%3:sgpr(s1) = G_TRUNC %1
|
||||
%4:scc(s1) = G_AND %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: and_s16_sgpr_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -474,8 +441,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0, $vgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
|
||||
; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
|
||||
@ -483,8 +452,10 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
@ -514,20 +485,24 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
||||
; WAVE32: liveins: $vgpr0
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_]]
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%1:vgpr(s32) = COPY $vgpr0
|
||||
%0:vgpr(s1) = G_TRUNC %1(s32)
|
||||
@ -556,8 +531,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
@ -566,10 +543,12 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_]]
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%1:vgpr(s32) = COPY $vgpr0
|
||||
%0:vgpr(s1) = G_TRUNC %1(s32)
|
||||
|
||||
@ -1,86 +1,6 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
|
||||
|
||||
---
|
||||
|
||||
name: anyext_scc_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_scc_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s32) = G_ANYEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: anyext_scc_s1_to_sgpr_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_scc_s1_to_sgpr_s64
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 1, implicit $scc
|
||||
; GCN: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s64) = G_ANYEXT %1
|
||||
$sgpr0_sgpr1 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: anyext_sgpr_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: $sgpr0 = COPY [[COPY]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_ANYEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: anyext_sgpr_s1_to_sgpr_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
|
||||
; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:sgpr(s64) = G_ANYEXT %1
|
||||
$sgpr0_sgpr1 = COPY %2
|
||||
...
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
|
||||
|
||||
---
|
||||
|
||||
@ -140,24 +60,38 @@ body: |
|
||||
|
||||
...
|
||||
|
||||
# vcc is an invalid extension source
|
||||
# ---
|
||||
|
||||
# name: anyext_vcc_s1_to_vgpr_s32
|
||||
# legalized: true
|
||||
# regBankSelected: true
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0
|
||||
|
||||
# %0:vgpr(s32) = COPY $vgpr0
|
||||
# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
# %2:vgpr(s32) = G_ANYEXT %1
|
||||
# $vgpr0 = COPY %2
|
||||
# ...
|
||||
|
||||
---
|
||||
|
||||
name: anyext_vcc_s1_to_vgpr_s32
|
||||
name: anyext_sgpr_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_vcc_s1_to_vgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY]], implicit $exec
|
||||
; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
|
||||
; GCN: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:vgpr(s32) = G_ANYEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: $sgpr0 = COPY [[COPY]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_ANYEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
@ -180,6 +114,24 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: anyext_sgpr_s1_to_vgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: $sgpr0 = COPY [[COPY]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_ANYEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: anyext_vgpr_s8_to_vgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -215,3 +167,23 @@ body: |
|
||||
$vgpr0 = COPY %2
|
||||
|
||||
...
|
||||
|
||||
# The source register already has an assigned register class that
|
||||
# should not be interpreted as vcc.
|
||||
---
|
||||
|
||||
name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: $sgpr0 = COPY [[COPY]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sreg_32(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_ANYEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
@ -29,7 +29,7 @@ body: |
|
||||
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
G_BRCOND %2, %bb.1
|
||||
|
||||
bb.1:
|
||||
@ -53,7 +53,7 @@ body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
%0:scc(s1) = G_IMPLICIT_DEF
|
||||
%0:sgpr(s32) = G_IMPLICIT_DEF
|
||||
G_BRCOND %0, %bb.1
|
||||
|
||||
bb.1:
|
||||
@ -76,7 +76,7 @@ body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
G_BRCOND undef %0:scc(s1), %bb.1
|
||||
G_BRCOND undef %0:sgpr(s32), %bb.1
|
||||
|
||||
bb.1:
|
||||
|
||||
@ -107,7 +107,7 @@ body: |
|
||||
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
G_BRCOND %2, %bb.1
|
||||
G_BR %bb.1
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@ body: |
|
||||
...
|
||||
---
|
||||
|
||||
name: copy_vcc_bank_scc_bank
|
||||
name: copy_vcc_bank_sgpr_bank
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
@ -39,34 +39,36 @@ body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
|
||||
|
||||
; WAVE64-LABEL: name: copy_vcc_bank_scc_bank
|
||||
; WAVE64-LABEL: name: copy_vcc_bank_sgpr_bank
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
|
||||
; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
|
||||
; WAVE32-LABEL: name: copy_vcc_bank_scc_bank
|
||||
; WAVE32-LABEL: name: copy_vcc_bank_sgpr_bank
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; WAVE32: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
|
||||
; WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
|
||||
; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:scc(s1) = COPY $scc
|
||||
%3:sgpr(s1) = COPY $scc
|
||||
%4:vcc(s1) = COPY %3
|
||||
%5:vgpr(s32) = G_SELECT %4, %1, %2
|
||||
G_STORE %5, %0 :: (store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
|
||||
name: copy_vcc_bank_scc_bank_2_uses
|
||||
name: copy_vcc_bank_sgpr_bank_2_uses
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
@ -74,31 +76,34 @@ body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
|
||||
|
||||
; WAVE64-LABEL: name: copy_vcc_bank_scc_bank_2_uses
|
||||
; WAVE64-LABEL: name: copy_vcc_bank_sgpr_bank_2_uses
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_1]], implicit $exec
|
||||
; WAVE64: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
|
||||
; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
|
||||
; WAVE32-LABEL: name: copy_vcc_bank_scc_bank_2_uses
|
||||
; WAVE32-LABEL: name: copy_vcc_bank_sgpr_bank_2_uses
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; WAVE32: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; WAVE32: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY3]]
|
||||
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY4]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
|
||||
; WAVE32: GLOBAL_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:scc(s1) = COPY $scc
|
||||
%3:sgpr(s1) = COPY $scc
|
||||
%4:vcc(s1) = COPY %3
|
||||
%5:vgpr(s32) = G_SELECT %4, %1, %2
|
||||
%6:vcc(s1) = COPY %3
|
||||
@ -207,68 +212,7 @@ body: |
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: copy_sgpr_s1_to_vcc
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
|
||||
body: |
|
||||
; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc
|
||||
; WAVE64: bb.0:
|
||||
; WAVE64: successors: %bb.1(0x80000000)
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: $vcc = COPY [[V_CMP_NE_U32_e64_]]
|
||||
; WAVE64: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; WAVE64: bb.1:
|
||||
; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc
|
||||
; WAVE32: bb.0:
|
||||
; WAVE32: successors: %bb.1(0x80000000)
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: $vcc_lo = COPY [[V_CMP_NE_U32_e64_]]
|
||||
; WAVE32: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
|
||||
; WAVE32: bb.1:
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:vcc(s1) = COPY %1
|
||||
G_BRCOND %2, %bb.1
|
||||
|
||||
bb.1:
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: copy_sgpr_s1_to_vcc_constrain
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1
|
||||
; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
|
||||
; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%2:vcc(s1) = COPY %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
# FIXME: This is malformed. There should never be a trunc to vcc.
|
||||
---
|
||||
|
||||
name: copy_s1_vcc_to_vcc
|
||||
@ -282,20 +226,17 @@ body: |
|
||||
|
||||
; WAVE64-LABEL: name: copy_s1_vcc_to_vcc
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_NE_U32_e64_]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
; WAVE32-LABEL: name: copy_s1_vcc_to_vcc
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s1) = G_TRUNC %0
|
||||
%1:vcc(s1) = G_TRUNC %0
|
||||
%2:vcc(s1) = COPY %1
|
||||
%3:vcc(s1) = COPY %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
|
||||
@ -797,3 +797,31 @@ body: |
|
||||
%2:vcc(s1) = G_FCMP floatpred(true), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_oeq_s32_vv_select_user
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
|
||||
%3:vgpr(s32) = G_SELECT %2, %0, %1
|
||||
S_ENDPGM 0, implicit %3
|
||||
...
|
||||
|
||||
@ -17,9 +17,9 @@ regBankSelected: true
|
||||
# GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
# GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7
|
||||
# GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc
|
||||
# GCN-NEXT: [[COND0:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
# GCN-NEXT: [[COND0:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
# GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc
|
||||
# GCN-NEXT: [[COND1:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
# GCN-NEXT: [[COND1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
# GCN: $scc = COPY [[COND0]]
|
||||
# GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc
|
||||
# GCN: $scc = COPY [[COND1]]
|
||||
@ -38,8 +38,8 @@ body: |
|
||||
%6:sgpr(s32) = COPY $sgpr5
|
||||
%7:sgpr(s32) = COPY $sgpr6
|
||||
%8:sgpr(s32) = COPY $sgpr7
|
||||
%9:scc(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%10:scc(s1) = G_ICMP intpred(ne), %5, %6
|
||||
%9:sgpr(s32) = G_ICMP intpred(ne), %1, %2
|
||||
%10:sgpr(s32) = G_ICMP intpred(ne), %5, %6
|
||||
%11:sgpr(s32) = G_SELECT %9, %7, %8
|
||||
%12:sgpr(s32) = G_SELECT %10, %3, %4
|
||||
%13:vgpr(s32) = COPY %11
|
||||
@ -74,16 +74,16 @@ body: |
|
||||
%2:sgpr(s32) = COPY $sgpr1
|
||||
%3:sgpr(s32) = COPY $sgpr2
|
||||
%4:sgpr(s32) = COPY $sgpr3
|
||||
%5:scc(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%6:scc(s1) = G_ICMP intpred(eq), %1, %2
|
||||
%7:scc(s1) = G_ICMP intpred(sgt), %1, %2
|
||||
%8:scc(s1) = G_ICMP intpred(sge), %1, %2
|
||||
%9:scc(s1) = G_ICMP intpred(slt), %1, %2
|
||||
%10:scc(s1) = G_ICMP intpred(sle), %1, %2
|
||||
%11:scc(s1) = G_ICMP intpred(ugt), %1, %2
|
||||
%12:scc(s1) = G_ICMP intpred(uge), %1, %2
|
||||
%13:scc(s1) = G_ICMP intpred(ult), %1, %2
|
||||
%14:scc(s1) = G_ICMP intpred(ule), %1, %2
|
||||
%5:sgpr(s32) = G_ICMP intpred(ne), %1, %2
|
||||
%6:sgpr(s32) = G_ICMP intpred(eq), %1, %2
|
||||
%7:sgpr(s32) = G_ICMP intpred(sgt), %1, %2
|
||||
%8:sgpr(s32) = G_ICMP intpred(sge), %1, %2
|
||||
%9:sgpr(s32) = G_ICMP intpred(slt), %1, %2
|
||||
%10:sgpr(s32) = G_ICMP intpred(sle), %1, %2
|
||||
%11:sgpr(s32) = G_ICMP intpred(ugt), %1, %2
|
||||
%12:sgpr(s32) = G_ICMP intpred(uge), %1, %2
|
||||
%13:sgpr(s32) = G_ICMP intpred(ult), %1, %2
|
||||
%14:sgpr(s32) = G_ICMP intpred(ule), %1, %2
|
||||
%15:sgpr(s32) = G_SELECT %5, %3, %4
|
||||
%16:sgpr(s32) = G_SELECT %6, %3, %4
|
||||
%17:sgpr(s32) = G_SELECT %7, %3, %4
|
||||
@ -325,11 +325,9 @@ body: |
|
||||
|
||||
%0:sgpr(p3) = COPY $sgpr0
|
||||
%1:sgpr(p3) = COPY $sgpr1
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:scc(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%4:sgpr(s32) = G_SEXT %2
|
||||
%5:sgpr(s32) = G_SEXT %3
|
||||
S_ENDPGM 0, implicit %4, implicit %5
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
%3:sgpr(s32) = G_ICMP intpred(ne), %0, %1
|
||||
S_ENDPGM 0, implicit %2, implicit %3
|
||||
|
||||
...
|
||||
|
||||
@ -351,8 +349,10 @@ body: |
|
||||
%1:vgpr(p3) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:vcc(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%4:vgpr(s32) = G_SEXT %2
|
||||
%5:vgpr(s32) = G_SEXT %3
|
||||
S_ENDPGM 0, implicit %4, implicit %5
|
||||
%4:vgpr(s1) = COPY %2
|
||||
%5:vgpr(s1) = COPY %3
|
||||
%6:vgpr(s32) = G_SEXT %4
|
||||
%7:vgpr(s32) = G_SEXT %5
|
||||
S_ENDPGM 0, implicit %6, implicit %7
|
||||
|
||||
...
|
||||
|
||||
@ -8,14 +8,14 @@
|
||||
|
||||
# ERR-NOT: remark
|
||||
|
||||
# GFX6-ERR: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(s64), %1:sgpr (in function: icmp_eq_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(ne), %0:sgpr(s64), %1:sgpr (in function: icmp_ne_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p0), %1:sgpr (in function: icmp_eq_p0_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p1), %1:sgpr (in function: icmp_eq_p1_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(eq), %0:sgpr(p999), %1:sgpr (in function: icmp_eq_p999_ss)
|
||||
# GFX6-ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(eq), %0:sgpr(s64), %1:sgpr (in function: icmp_eq_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(ne), %0:sgpr(s64), %1:sgpr (in function: icmp_ne_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(eq), %0:sgpr(p0), %1:sgpr (in function: icmp_eq_p0_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(eq), %0:sgpr(p1), %1:sgpr (in function: icmp_eq_p1_ss)
|
||||
# GFX6-ERR-NEXT: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(eq), %0:sgpr(p999), %1:sgpr (in function: icmp_eq_p999_ss)
|
||||
|
||||
# GFX8-ERR: remark: <unknown>:0:0: cannot select: %2:scc(s1) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
|
||||
# GFX8-ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_ICMP intpred(slt), %0:sgpr(s64), %1:sgpr (in function: icmp_slt_s64_ss)
|
||||
|
||||
# ERR-NOT: remark
|
||||
|
||||
@ -33,22 +33,16 @@ body: |
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[COPY2]]
|
||||
; GFX6-LABEL: name: icmp_eq_s64_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -66,22 +60,16 @@ body: |
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX8: S_CMP_LG_U64 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[COPY2]]
|
||||
; GFX6-LABEL: name: icmp_ne_s64_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%2:sgpr(s32) = G_ICMP intpred(ne), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -97,24 +85,17 @@ body: |
|
||||
; GFX8-LABEL: name: icmp_slt_s64_ss
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX8: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
; GFX6-LABEL: name: icmp_slt_s64_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(slt), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%2:sgpr(s32) = G_ICMP intpred(slt), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -131,19 +112,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_eq_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -160,19 +144,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_NE_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_NE_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_ne_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_NE_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_NE_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -189,19 +176,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_GT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_I64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GT_I64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_sgt_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_GT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_I64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GT_I64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(sgt), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -218,19 +208,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_GE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_I64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GE_I64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_sge_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_GE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_I64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GE_I64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(sge), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -247,19 +240,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_I64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LT_I64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_slt_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_LT_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_I64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LT_I64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(slt), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -276,19 +272,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_LE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_I64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LE_I64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_sle_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_LE_I64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_I64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_I64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LE_I64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(sle), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -305,19 +304,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_GT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GT_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_ugt_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_GT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GT_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GT_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(ugt), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -334,19 +336,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_GE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GE_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_uge_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_GE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_GE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_GE_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_GE_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(uge), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -363,19 +368,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LT_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_ult_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LT_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LT_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LT_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(ult), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -392,19 +400,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_LE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LE_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_ule_s64_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_LE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_LE_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_LE_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_LE_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(ule), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -422,23 +433,16 @@ body: |
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[COPY2]]
|
||||
; GFX6-LABEL: name: icmp_eq_p0_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(p0) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(p0) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
@ -455,22 +459,16 @@ body: |
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[COPY2]]
|
||||
; GFX6-LABEL: name: icmp_eq_p1_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p1), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](p1), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(p1) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -488,22 +486,16 @@ body: |
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GFX8: S_CMP_EQ_U64 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
; GFX8: S_ENDPGM 0, implicit [[COPY2]]
|
||||
; GFX6-LABEL: name: icmp_eq_p999_ss
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p999) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sgpr(p999) = COPY $sgpr2_sgpr3
|
||||
; GFX6: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](p999), [[COPY1]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[ICMP]](s1)
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32(s32) = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_CSELECT_B32_]](s32)
|
||||
; GFX6: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](p999), [[COPY1]]
|
||||
; GFX6: S_ENDPGM 0, implicit [[ICMP]](s32)
|
||||
%0:sgpr(p999) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(p999) = COPY $sgpr2_sgpr3
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:sgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -520,19 +512,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_eq_p0_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(p0) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(p0) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -549,19 +544,22 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_eq_p1_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(p1) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -578,18 +576,21 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX8: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX8: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX8: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
; GFX6-LABEL: name: icmp_eq_p999_vv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY]], [[COPY1]], implicit $exec
|
||||
; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U64_e64_]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CMP_EQ_U64_e64_]]
|
||||
; GFX6: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY2]], implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_AND_B32_e32_]]
|
||||
%0:vgpr(p999) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(p999) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%3:vgpr(s32) = G_ZEXT %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
%3:vgpr(s1) = COPY %2
|
||||
%4:vgpr(s32) = G_ZEXT %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
@ -2,10 +2,6 @@
|
||||
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
|
||||
# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
|
||||
|
||||
# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash.
|
||||
# ERR: remark: <unknown>:0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc)
|
||||
# ERR-NOT: remark
|
||||
|
||||
---
|
||||
|
||||
name: implicit_def_s32_sgpr
|
||||
@ -177,21 +173,6 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: implicit_def_s1_scc
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: implicit_def_s1_scc
|
||||
; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
|
||||
; GCN: S_ENDPGM 0, implicit [[DEF]]
|
||||
%0:scc(s1) = G_IMPLICIT_DEF
|
||||
S_ENDPGM 0, implicit %0
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: implicit_def_s1_vcc
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
@ -41,6 +41,7 @@ body: |
|
||||
S_ENDPGM 0, implicit %5
|
||||
...
|
||||
|
||||
# Should fail to select
|
||||
---
|
||||
|
||||
name: or_s1_sgpr_sgpr_sgpr
|
||||
@ -74,40 +75,6 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: or_s1_scc_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; WAVE64-LABEL: name: or_s1_scc_sgpr_sgpr
|
||||
; WAVE64: liveins: $sgpr0, $sgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE64: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
|
||||
; WAVE32-LABEL: name: or_s1_scc_sgpr_sgpr
|
||||
; WAVE32: liveins: $sgpr0, $sgpr1
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE32: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s1) = G_TRUNC %0
|
||||
%3:sgpr(s1) = G_TRUNC %1
|
||||
%4:scc(s1) = G_OR %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: or_s16_sgpr_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -474,8 +441,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0, $vgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
|
||||
; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
|
||||
@ -483,8 +452,10 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
@ -514,18 +485,22 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
|
||||
; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
||||
; WAVE32: liveins: $vgpr0
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
@ -556,8 +531,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
@ -566,9 +543,11 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%1:vgpr(s32) = COPY $vgpr0
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
# RUN: llc -march=amdgcn -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=ERR
|
||||
# ERR: remark: <unknown>:0:0: cannot select: %7:scc(s1) = G_PHI %4:scc(s1), %bb.0, %6:scc(s1), %bb.1 (in function: g_phi_scc_s1_sbranch)
|
||||
|
||||
---
|
||||
name: g_phi_scc_s1_sbranch
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1, $sgpr2
|
||||
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %0, %3
|
||||
%5:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %5(s1), %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
%6:scc(s1) = G_ICMP intpred(eq), %1, %3
|
||||
G_BR %bb.2
|
||||
|
||||
bb.2:
|
||||
%7:scc(s1) = G_PHI %4, %bb.0, %6, %bb.1
|
||||
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %7
|
||||
|
||||
...
|
||||
@ -35,8 +35,8 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -85,8 +85,8 @@ body: |
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -134,8 +134,8 @@ body: |
|
||||
%1:vgpr(s32) = COPY $vgpr0
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -184,8 +184,8 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:sgpr(s32) = COPY $sgpr1
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -233,8 +233,8 @@ body: |
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%2:sgpr(s32) = COPY $sgpr4
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -282,8 +282,8 @@ body: |
|
||||
%1:vgpr(<2 x s16>) = COPY $vgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -333,8 +333,8 @@ body: |
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:vcc(s1) = G_ICMP intpred(eq), %0, %3
|
||||
%5:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %5(s1), %bb.1
|
||||
%5:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %5, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -381,8 +381,8 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
@ -431,8 +431,8 @@ body: |
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4, %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
|
||||
@ -16,7 +16,7 @@ body: |
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY4]]
|
||||
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
|
||||
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
|
||||
@ -24,7 +24,7 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
%3:sgpr(s64) = COPY $sgpr4_sgpr5
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
%5:sgpr(s64) = G_SELECT %4, %2, %3
|
||||
S_ENDPGM 0, implicit %5
|
||||
|
||||
@ -45,7 +45,7 @@ body: |
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY4]]
|
||||
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
|
||||
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
|
||||
@ -53,7 +53,7 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
%3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
%5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3
|
||||
S_ENDPGM 0, implicit %5
|
||||
|
||||
@ -74,7 +74,7 @@ body: |
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
|
||||
; GCN: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY4]]
|
||||
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
@ -84,7 +84,7 @@ body: |
|
||||
%3:sgpr(s32) = COPY $sgpr3
|
||||
%4:sgpr(s16) = G_TRUNC %0
|
||||
%5:sgpr(s16) = G_TRUNC %1
|
||||
%6:scc(s1) = G_ICMP intpred(eq), %2, %3
|
||||
%6:sgpr(s32) = G_ICMP intpred(eq), %2, %3
|
||||
%7:sgpr(s16) = G_SELECT %6, %4, %5
|
||||
S_ENDPGM 0, implicit %7
|
||||
|
||||
@ -105,7 +105,7 @@ body: |
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY4]]
|
||||
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
|
||||
; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
|
||||
@ -113,7 +113,7 @@ body: |
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(<2 x s16>) = COPY $sgpr2
|
||||
%3:sgpr(<2 x s16>) = COPY $sgpr3
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
|
||||
%5:sgpr(<2 x s16>) = G_SELECT %4, %2, %3
|
||||
S_ENDPGM 0, implicit %5
|
||||
|
||||
|
||||
@ -3,50 +3,6 @@
|
||||
|
||||
---
|
||||
|
||||
name: sext_scc_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: sext_scc_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, -1, implicit $scc
|
||||
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s32) = G_SEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: sext_scc_s1_to_sgpr_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: sext_scc_s1_to_sgpr_s64
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, -1, implicit $scc
|
||||
; GCN: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s64) = G_SEXT %1
|
||||
$sgpr0_sgpr1 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: sext_sgpr_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -146,25 +102,20 @@ body: |
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# ---
|
||||
|
||||
name: sext_vcc_s1_to_vgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
# name: sext_vcc_s1_to_vgpr_s32
|
||||
# legalized: true
|
||||
# regBankSelected: true
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0
|
||||
|
||||
; GCN-LABEL: name: sext_vcc_s1_to_vgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY]], implicit $exec
|
||||
; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, [[V_CMP_EQ_U32_e64_]], implicit $exec
|
||||
; GCN: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:vgpr(s32) = G_SEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
# %0:vgpr(s32) = COPY $vgpr0
|
||||
# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
# %2:vgpr(s32) = G_SEXT %1
|
||||
# $vgpr0 = COPY %2
|
||||
# ...
|
||||
|
||||
---
|
||||
|
||||
@ -224,3 +175,22 @@ body: |
|
||||
$vgpr0 = COPY %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: sext_sgpr_reg_class_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: sext_sgpr_reg_class_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
|
||||
; GCN: $sgpr0 = COPY [[S_BFE_I32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sreg_32(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_SEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
@ -371,3 +371,19 @@ body: |
|
||||
%1:vgpr(s256) = G_TRUNC %0
|
||||
S_ENDPGM 0, implicit %1
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: trunc_sgpr_s32_to_s1_use
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
%0:sgpr(s32) =COPY $sgpr0
|
||||
%1:sgpr(s32) =COPY $sgpr1
|
||||
%2:sgpr(s1) = G_TRUNC %0
|
||||
%3:sgpr(s32) = G_SELECT %2, %0, %1
|
||||
S_ENDPGM 0, implicit %3
|
||||
...
|
||||
|
||||
@ -17,7 +17,7 @@ body: |
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -25,7 +25,7 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -33,7 +33,7 @@ body: |
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX9: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX9: $scc = COPY [[COPY2]]
|
||||
; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -42,13 +42,13 @@ body: |
|
||||
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX10: $scc = COPY [[COPY2]]
|
||||
; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX10: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32), %3:scc(s1) = G_UADDO %0, %1
|
||||
%2:sgpr(s32), %3:sgpr(s32) = G_UADDO %0, %1
|
||||
%4:sgpr(s32) = G_SELECT %3, %0, %1
|
||||
S_ENDPGM 0, implicit %2, implicit %4
|
||||
...
|
||||
|
||||
@ -17,7 +17,7 @@ body: |
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX6: $scc = COPY [[COPY2]]
|
||||
; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -25,7 +25,7 @@ body: |
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX8: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX8: $scc = COPY [[COPY2]]
|
||||
; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -33,7 +33,7 @@ body: |
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX9: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX9: $scc = COPY [[COPY2]]
|
||||
; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
@ -42,13 +42,13 @@ body: |
|
||||
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
|
||||
; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GFX10: $scc = COPY [[COPY2]]
|
||||
; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
|
||||
; GFX10: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32), %3:scc(s1) = G_USUBO %0, %1
|
||||
%2:sgpr(s32), %3:sgpr(s32) = G_USUBO %0, %1
|
||||
%4:sgpr(s32) = G_SELECT %3, %0, %1
|
||||
S_ENDPGM 0, implicit %2, implicit %4
|
||||
...
|
||||
|
||||
@ -41,6 +41,8 @@ body: |
|
||||
S_ENDPGM 0, implicit %5
|
||||
...
|
||||
|
||||
# Should fail to select
|
||||
|
||||
---
|
||||
|
||||
name: xor_s1_sgpr_sgpr_sgpr
|
||||
@ -74,40 +76,6 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: xor_s1_scc_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; WAVE64-LABEL: name: xor_s1_scc_sgpr_sgpr
|
||||
; WAVE64: liveins: $sgpr0, $sgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE64: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[XOR]](s1)
|
||||
; WAVE32-LABEL: name: xor_s1_scc_sgpr_sgpr
|
||||
; WAVE32: liveins: $sgpr0, $sgpr1
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE32: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[XOR]](s1)
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s1) = G_TRUNC %0
|
||||
%3:sgpr(s1) = G_TRUNC %1
|
||||
%4:scc(s1) = G_XOR %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: xor_s16_sgpr_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -474,8 +442,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0, $vgpr1
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
|
||||
; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
|
||||
@ -483,8 +453,10 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
|
||||
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
@ -514,18 +486,22 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]]
|
||||
; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
|
||||
; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
|
||||
; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY2]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY3]]
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
|
||||
; WAVE32: liveins: $vgpr0
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
@ -556,8 +532,10 @@ body: |
|
||||
; WAVE64: liveins: $vgpr0
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
|
||||
@ -566,9 +544,11 @@ body: |
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
|
||||
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
|
||||
; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
|
||||
; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[S_MOV_B32_]], implicit-def $scc
|
||||
; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
|
||||
; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%1:vgpr(s32) = COPY $vgpr0
|
||||
|
||||
@ -3,50 +3,6 @@
|
||||
|
||||
---
|
||||
|
||||
name: zext_scc_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: zext_scc_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 0, 1, implicit $scc
|
||||
; GCN: $sgpr0 = COPY [[S_CSELECT_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s32) = G_ZEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: zext_scc_s1_to_sgpr_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: zext_scc_s1_to_sgpr_s64
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY]], implicit-def $scc
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY1]]
|
||||
; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 0, 1, implicit $scc
|
||||
; GCN: $sgpr0_sgpr1 = COPY [[S_CSELECT_B64_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:scc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:sgpr(s64) = G_ZEXT %1
|
||||
$sgpr0_sgpr1 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: zext_sgpr_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -147,25 +103,20 @@ body: |
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# ---
|
||||
|
||||
name: zext_vcc_s1_to_vgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
# name: zext_vcc_s1_to_vgpr_s32
|
||||
# legalized: true
|
||||
# regBankSelected: true
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0
|
||||
|
||||
; GCN-LABEL: name: zext_vcc_s1_to_vgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY]], implicit $exec
|
||||
; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_EQ_U32_e64_]], implicit $exec
|
||||
; GCN: $vgpr0 = COPY [[V_CNDMASK_B32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
%2:vgpr(s32) = G_ZEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
# %0:vgpr(s32) = COPY $vgpr0
|
||||
# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
|
||||
# %2:vgpr(s32) = G_ZEXT %1
|
||||
# $vgpr0 = COPY %2
|
||||
# ...
|
||||
|
||||
---
|
||||
|
||||
@ -225,3 +176,22 @@ body: |
|
||||
$vgpr0 = COPY %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: zext_sgpr_reg_class_s1_to_sgpr_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0
|
||||
|
||||
; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
|
||||
; GCN: $sgpr0 = COPY [[S_AND_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sreg_32(s1) = G_TRUNC %0
|
||||
%2:sgpr(s32) = G_ZEXT %1
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
@ -34,31 +34,64 @@ body: |
|
||||
|
||||
---
|
||||
|
||||
name: legal_brcond_scc
|
||||
name: legal_brcond_sgpr_s1
|
||||
|
||||
body: |
|
||||
; WAVE64-LABEL: name: legal_brcond_scc
|
||||
; WAVE64-LABEL: name: legal_brcond_sgpr_s1
|
||||
; WAVE64: bb.0:
|
||||
; WAVE64: successors: %bb.1(0x80000000)
|
||||
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE64: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
||||
; WAVE64: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1
|
||||
; WAVE64: bb.1:
|
||||
; WAVE32-LABEL: name: legal_brcond_scc
|
||||
; WAVE32-LABEL: name: legal_brcond_sgpr_s1
|
||||
; WAVE32: bb.0:
|
||||
; WAVE32: successors: %bb.1(0x80000000)
|
||||
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; WAVE32: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
||||
; WAVE32: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1
|
||||
; WAVE32: bb.1:
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:scc(s1) = G_ICMP intpred(eq), %0, %1
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
G_BRCOND %2, %bb.1
|
||||
|
||||
bb.1:
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: legal_brcond_sgpr_s32
|
||||
|
||||
body: |
|
||||
; WAVE64-LABEL: name: legal_brcond_sgpr_s32
|
||||
; WAVE64: bb.0:
|
||||
; WAVE64: successors: %bb.1(0x80000000)
|
||||
; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
||||
; WAVE64: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE64: G_BRCOND [[ICMP]](s32), %bb.1
|
||||
; WAVE64: bb.1:
|
||||
; WAVE32-LABEL: name: legal_brcond_sgpr_s32
|
||||
; WAVE32: bb.0:
|
||||
; WAVE32: successors: %bb.1(0x80000000)
|
||||
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
||||
; WAVE32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE32: G_BRCOND [[ICMP]](s32), %bb.1
|
||||
; WAVE32: bb.1:
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_ICMP intpred(eq), %0, %1
|
||||
G_BRCOND %2, %bb.1
|
||||
|
||||
bb.1:
|
||||
|
||||
@ -9,6 +9,9 @@ define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
|
||||
; GCN-NEXT: ; implicit-def: $vcc_hi
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_cmp_eq_u32 s1, 0
|
||||
; GCN-NEXT: s_cselect_b32 s1, 1, 0
|
||||
; GCN-NEXT: s_and_b32 s1, s1, 1
|
||||
; GCN-NEXT: s_cmp_lg_u32 s1, 0
|
||||
; GCN-NEXT: s_cbranch_scc0 BB0_2
|
||||
; GCN-NEXT: ; %bb.1: ; %mid
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
|
||||
@ -8,6 +8,9 @@ define amdgpu_kernel void @test_wave64(i32 %arg0, i64 %saved) {
|
||||
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_cmp_eq_u32 s2, 0
|
||||
; GCN-NEXT: s_cselect_b32 s2, 1, 0
|
||||
; GCN-NEXT: s_and_b32 s2, s2, 1
|
||||
; GCN-NEXT: s_cmp_lg_u32 s2, 0
|
||||
; GCN-NEXT: s_cbranch_scc0 BB0_2
|
||||
; GCN-NEXT: ; %bb.1: ; %mid
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
|
||||
@ -10,6 +10,7 @@ define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_cmp_eq_u32 s0, 0
|
||||
; GCN-NEXT: s_cselect_b32 s0, 1, 0
|
||||
; GCN-NEXT: s_and_b32 s0, 1, s0
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
|
||||
; GCN-NEXT: s_or_b32 s0, s0, s1
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
|
||||
@ -9,6 +9,7 @@ define amdgpu_kernel void @test_wave64(i32 %arg0, [8 x i32], i64 %saved) {
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_cmp_eq_u32 s2, 0
|
||||
; GCN-NEXT: s_cselect_b32 s2, 1, 0
|
||||
; GCN-NEXT: s_and_b32 s2, 1, s2
|
||||
; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
|
||||
; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s0
|
||||
|
||||
@ -66,6 +66,9 @@ define amdgpu_kernel void @is_private_sgpr(i8* %ptr) {
|
||||
; CI-NEXT: s_load_dword s0, s[4:5], 0x11
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: s_cmp_eq_u32 s1, s0
|
||||
; CI-NEXT: s_cselect_b32 s0, 1, 0
|
||||
; CI-NEXT: s_and_b32 s0, s0, 1
|
||||
; CI-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; CI-NEXT: s_cbranch_scc0 BB1_2
|
||||
; CI-NEXT: ; %bb.1: ; %bb0
|
||||
; CI-NEXT: v_mov_b32_e32 v0, 0
|
||||
@ -80,6 +83,9 @@ define amdgpu_kernel void @is_private_sgpr(i8* %ptr) {
|
||||
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
|
||||
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
|
||||
; GFX9-NEXT: s_cmp_eq_u32 s1, s0
|
||||
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
|
||||
; GFX9-NEXT: s_and_b32 s0, s0, 1
|
||||
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GFX9-NEXT: s_cbranch_scc0 BB1_2
|
||||
; GFX9-NEXT: ; %bb.1: ; %bb0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, 0
|
||||
|
||||
@ -66,6 +66,9 @@ define amdgpu_kernel void @is_local_sgpr(i8* %ptr) {
|
||||
; CI-NEXT: s_load_dword s0, s[4:5], 0x10
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: s_cmp_eq_u32 s1, s0
|
||||
; CI-NEXT: s_cselect_b32 s0, 1, 0
|
||||
; CI-NEXT: s_and_b32 s0, s0, 1
|
||||
; CI-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; CI-NEXT: s_cbranch_scc0 BB1_2
|
||||
; CI-NEXT: ; %bb.1: ; %bb0
|
||||
; CI-NEXT: v_mov_b32_e32 v0, 0
|
||||
@ -80,6 +83,9 @@ define amdgpu_kernel void @is_local_sgpr(i8* %ptr) {
|
||||
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
|
||||
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
|
||||
; GFX9-NEXT: s_cmp_eq_u32 s1, s0
|
||||
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
|
||||
; GFX9-NEXT: s_and_b32 s0, s0, 1
|
||||
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
|
||||
; GFX9-NEXT: s_cbranch_scc0 BB1_2
|
||||
; GFX9-NEXT: ; %bb.1: ; %bb0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, 0
|
||||
|
||||
@ -15,10 +15,11 @@ body: |
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
|
||||
@ -12,8 +12,9 @@ body: |
|
||||
; CHECK-LABEL: name: kill_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.kill), [[COPY2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
|
||||
@ -12,8 +12,9 @@ body: |
|
||||
; CHECK-LABEL: name: wqm_vote_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
|
||||
|
||||
---
|
||||
name: and_s1_sgpr_sgpr
|
||||
@ -9,18 +9,15 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_sgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_sgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_sgpr_sgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AND]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -35,24 +32,18 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_scc_scc
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; FAST: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_scc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; CHECK-LABEL: name: and_s1_scc_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AND]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -68,18 +59,12 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; FAST-LABEL: name: and_s1_vgpr_vgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_vgpr_vgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_vgpr_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -94,20 +79,13 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; FAST-LABEL: name: and_s1_vcc_vcc
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_vcc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
; CHECK-LABEL: name: and_s1_vcc_vcc
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -123,18 +101,13 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $vgpr0
|
||||
; FAST-LABEL: name: and_s1_sgpr_vgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_sgpr_vgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_sgpr_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[TRUNC1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -149,18 +122,13 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr0
|
||||
; FAST-LABEL: name: and_s1_vgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_vgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_vgpr_sgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[TRUNC]], [[COPY2]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -176,22 +144,15 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $vgpr0
|
||||
; FAST-LABEL: name: and_s1_scc_vcc
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_vcc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
|
||||
; CHECK-LABEL: name: and_s1_scc_vcc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -207,20 +168,13 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; FAST-LABEL: name: and_s1_vcc_scc
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_scc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
; CHECK-LABEL: name: and_s1_vcc_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -231,124 +185,63 @@ body: |
|
||||
|
||||
|
||||
# Test with a known result bank
|
||||
---
|
||||
name: and_s1_vcc_sgpr_sgpr
|
||||
legalized: true
|
||||
# ---
|
||||
# name: and_s1_vcc_sgpr_sgpr
|
||||
# legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_vcc_sgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_sgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[AND]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_AND %2, %3
|
||||
...
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $sgpr0, $sgpr1
|
||||
|
||||
---
|
||||
name: and_s1_vcc_vgpr_vgpr
|
||||
legalized: true
|
||||
# %0:_(s32) = COPY $sgpr0
|
||||
# %1:_(s32) = COPY $sgpr1
|
||||
# %2:_(s1) = G_TRUNC %0
|
||||
# %3:_(s1) = G_TRUNC %1
|
||||
# %4:vcc(s1) = G_AND %2, %3
|
||||
# ...
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; FAST-LABEL: name: and_s1_vcc_vgpr_vgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_vgpr_vgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_AND %2, %3
|
||||
...
|
||||
# ---
|
||||
# name: and_s1_vcc_vgpr_vgpr
|
||||
# legalized: true
|
||||
|
||||
---
|
||||
name: and_s1_vcc_vgpr_sgpr
|
||||
legalized: true
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0, $vgpr1
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
; FAST-LABEL: name: and_s1_vcc_vgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_vgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_AND %2, %3
|
||||
...
|
||||
# %0:_(s32) = COPY $vgpr0
|
||||
# %1:_(s32) = COPY $vgpr1
|
||||
# %2:_(s1) = G_TRUNC %0
|
||||
# %3:_(s1) = G_TRUNC %1
|
||||
# %4:vcc(s1) = G_AND %2, %3
|
||||
# ...
|
||||
|
||||
---
|
||||
name: and_s1_vcc_sgpr_vgpr
|
||||
legalized: true
|
||||
# ---
|
||||
# name: and_s1_vcc_vgpr_sgpr
|
||||
# legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
; FAST-LABEL: name: and_s1_vcc_sgpr_vgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_vcc_sgpr_vgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_AND %2, %3
|
||||
...
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0, $sgpr0
|
||||
# %0:_(s32) = COPY $vgpr0
|
||||
# %1:_(s32) = COPY $sgpr0
|
||||
# %2:_(s1) = G_TRUNC %0
|
||||
# %3:_(s1) = G_TRUNC %1
|
||||
# %4:vcc(s1) = G_AND %2, %3
|
||||
# ...
|
||||
|
||||
# ---
|
||||
# name: and_s1_vcc_sgpr_vgpr
|
||||
# legalized: true
|
||||
|
||||
# body: |
|
||||
# bb.0:
|
||||
# liveins: $vgpr0, $sgpr0
|
||||
# %0:_(s32) = COPY $sgpr0
|
||||
# %1:_(s32) = COPY $vgpr0
|
||||
# %2:_(s1) = G_TRUNC %0
|
||||
# %3:_(s1) = G_TRUNC %1
|
||||
# %4:vcc(s1) = G_AND %2, %3
|
||||
# ...
|
||||
|
||||
---
|
||||
name: and_s1_vgpr_sgpr_sgpr
|
||||
@ -357,18 +250,15 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_vgpr_sgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_vgpr_sgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_vgpr_sgpr_sgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[AND]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -383,145 +273,18 @@ legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_sgpr_sgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_sgpr_sgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK-LABEL: name: and_s1_sgpr_sgpr_sgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[AND]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:sgpr(s1) = G_AND %2, %3
|
||||
...
|
||||
|
||||
---
|
||||
name: and_s1_scc_sgpr_sgpr
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_scc_sgpr_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_sgpr_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
%3:_(s1) = G_TRUNC %1
|
||||
%4:scc(s1) = G_AND %2, %3
|
||||
...
|
||||
|
||||
---
|
||||
name: and_s1_scc_scc_scc
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_scc_scc_scc
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; FAST: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_scc_scc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(s1) = G_ICMP intpred(ne), %0, %2
|
||||
%4:_(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%5:scc(s1) = G_AND %3, %4
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: and_s1_scc_sgpr_scc
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_scc_sgpr_scc
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[COPY2]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_sgpr_scc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[COPY2]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(s1) = G_TRUNC %0
|
||||
%4:_(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%5:scc(s1) = G_AND %3, %4
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: and_s1_scc_scc_sgpr
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; FAST-LABEL: name: and_s1_scc_scc_sgpr
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[TRUNC]]
|
||||
; GREEDY-LABEL: name: and_s1_scc_scc_sgpr
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[TRUNC]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
%3:_(s1) = G_ICMP intpred(ne), %0, %2
|
||||
%4:_(s1) = G_TRUNC %1
|
||||
%5:scc(s1) = G_AND %3, %4
|
||||
|
||||
...
|
||||
|
||||
@ -40,8 +40,9 @@ body: |
|
||||
; CHECK-LABEL: name: anyext_s1_to_s16_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[ICMP]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -58,8 +59,9 @@ body: |
|
||||
; CHECK-LABEL: name: anyext_s1_to_s32_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[ICMP]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -76,8 +78,9 @@ body: |
|
||||
; CHECK-LABEL: name: anyext_s1_to_s64_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[ICMP]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -195,7 +198,7 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: anyext_s1_to_s16_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
@ -211,7 +214,7 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: anyext_s1_to_s32_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
@ -227,7 +230,7 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: anyext_s1_to_s64_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s64) = G_ANYEXT [[TRUNC]](s1)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
|
||||
@ -34,8 +34,10 @@ body: |
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[ZEXT]](s32), %bb.1
|
||||
; CHECK: bb.1:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
@ -57,8 +59,8 @@ body: |
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
|
||||
; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[ZEXT]](s32), %bb.1
|
||||
; CHECK: bb.1:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
@ -78,9 +80,8 @@ body: |
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
|
||||
; CHECK: bb.1:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
@ -104,11 +105,10 @@ body: |
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
|
||||
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
|
||||
; CHECK: bb.2:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
@ -134,9 +134,8 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
|
||||
; CHECK: bb.2:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
@ -161,10 +160,9 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: S_NOP 0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: G_BRCOND [[COPY1]](s1), %bb.1
|
||||
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
|
||||
; CHECK: bb.2:
|
||||
bb.0.entry:
|
||||
successors: %bb.1
|
||||
|
||||
@ -14,11 +14,13 @@ body: |
|
||||
; GFX7-LABEL: name: icmp_eq_s32_ss
|
||||
; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GFX7: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; GFX7: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; GFX7: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GFX8-LABEL: name: icmp_eq_s32_ss
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GFX8: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -98,7 +100,8 @@ body: |
|
||||
; GFX8-LABEL: name: icmp_eq_s64_ss
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX8: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
%0:_(s64) = COPY $sgpr0_sgpr1
|
||||
%1:_(s64) = COPY $sgpr2_sgpr3
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -178,7 +181,8 @@ body: |
|
||||
; GFX8-LABEL: name: icmp_ne_s64_ss
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GFX8: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
|
||||
; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
%0:_(s64) = COPY $sgpr0_sgpr1
|
||||
%1:_(s64) = COPY $sgpr2_sgpr3
|
||||
%2:_(s1) = G_ICMP intpred(ne), %0, %1
|
||||
|
||||
@ -78,12 +78,15 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:scc(s1) = G_OR [[COPY2]], [[COPY3]]
|
||||
; CHECK: S_NOP 0, implicit [[OR]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[OR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -128,9 +131,10 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP1]]
|
||||
; CHECK: S_NOP 0, implicit [[OR]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
@ -153,8 +157,11 @@ body: |
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK: S_NOP 0, implicit [[OR]](s1)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[OR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -174,10 +181,13 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[COPY2]]
|
||||
; CHECK: S_NOP 0, implicit [[OR]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[OR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -14,15 +14,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32)
|
||||
; GREEDY-LABEL: name: sadde_s32_sss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -43,18 +49,20 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
; GREEDY-LABEL: name: sadde_s32_vss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
@ -74,20 +82,18 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
; GREEDY-LABEL: name: sadde_s32_ssv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
@ -135,17 +141,17 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32)
|
||||
; GREEDY-LABEL: name: sadde_s32_sss_noscc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
|
||||
@ -13,15 +13,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_s32_scc_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -41,17 +45,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY4]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_s32_scc_sv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY4]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -72,17 +80,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY3]], [[COPY5]]
|
||||
; GREEDY-LABEL: name: select_s32_scc_vs
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY3]], [[COPY5]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -102,15 +114,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_s32_scc_vv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
@ -250,15 +266,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY $sgpr4_sgpr5
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_s64_sss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY $sgpr4_sgpr5
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s64) = COPY $sgpr2_sgpr3
|
||||
@ -278,22 +298,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_s64_ssv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -315,22 +339,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_s64_svs
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -351,22 +379,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_s64_svv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -531,15 +563,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr4_sgpr5
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(<2 x s32>) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(<2 x s32>) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_v2s32_scc_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr4_sgpr5
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(<2 x s32>) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(<2 x s32>) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
@ -559,22 +595,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_v2s32_scc_sv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -596,22 +636,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_v2s32_scc_vs
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -632,22 +676,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_v2s32_scc_vv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -812,15 +860,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(<4 x s16>) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(<4 x s16>) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_v4s16_scc_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(<4 x s16>) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(<4 x s16>) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
@ -840,22 +892,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
; GREEDY-LABEL: name: select_v4s16_scc_sv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -877,22 +933,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
; GREEDY-LABEL: name: select_v4s16_scc_vs
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -913,22 +973,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
; GREEDY-LABEL: name: select_v4s16_scc_vv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(<2 x s16>), [[UV1:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(<2 x s16>), [[UV3:%[0-9]+]]:vgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY3]](<4 x s16>)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(<2 x s16>) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[SELECT]](<2 x s16>), [[SELECT1]](<2 x s16>)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -1094,15 +1158,19 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:sgpr(p1) = COPY $sgpr4_sgpr5
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(p1) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(p1) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
; GREEDY-LABEL: name: select_p1_scc_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(p1) = COPY $sgpr4_sgpr5
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(p1) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(p1) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(p1) = COPY $sgpr2_sgpr3
|
||||
@ -1122,22 +1190,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_p1_scc_sv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -1159,22 +1231,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_p1_scc_vs
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -1195,22 +1271,26 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr2_vgpr3
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; FAST: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
; GREEDY-LABEL: name: select_p1_scc_vv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(p1) = COPY $vgpr2_vgpr3
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p1)
|
||||
; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
|
||||
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
|
||||
; GREEDY: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -1374,16 +1454,14 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
|
||||
; GREEDY-LABEL: name: select_s32_vgpr_vv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(s32) = COPY $vgpr2
|
||||
@ -1401,20 +1479,18 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY4]]
|
||||
; GREEDY-LABEL: name: select_s32_vgpr_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY4]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
%2:_(s32) = COPY $sgpr1
|
||||
@ -1519,17 +1595,15 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY1]], [[COPY2]]
|
||||
; GREEDY-LABEL: name: select_s32_sgpr_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY1]], [[COPY2]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
|
||||
@ -59,11 +59,12 @@ body: |
|
||||
; CHECK-LABEL: name: sext_s1_to_s16_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -80,10 +81,12 @@ body: |
|
||||
; CHECK-LABEL: name: sext_s1_to_s32_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -100,10 +103,12 @@ body: |
|
||||
; CHECK-LABEL: name: sext_s1_to_s64_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[ASHR:%[0-9]+]]:sgpr(s64) = G_ASHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -239,11 +244,11 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: sext_s1_to_s16_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15
|
||||
; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s16) = G_SEXT %1
|
||||
@ -258,11 +263,10 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: sext_s1_to_s32_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
|
||||
; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SHL]], [[C]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s32) = G_SEXT %1
|
||||
@ -277,11 +281,12 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: sext_s1_to_s64_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[SEXT:%[0-9]+]]:vgpr(s32) = G_SEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
|
||||
; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT]], [[C]](s32)
|
||||
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT]](s32), [[ASHR]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 -1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)
|
||||
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[COPY1]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s64) = G_SEXT %1
|
||||
|
||||
@ -13,13 +13,13 @@ body: |
|
||||
; FAST-LABEL: name: smax_s32_ss
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY-LABEL: name: smax_s32_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_SMAX %0, %1
|
||||
@ -101,14 +101,14 @@ body: |
|
||||
; FAST-LABEL: name: smax_s32_ss_vgpr_use
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; FAST: $vgpr0 = COPY [[SELECT]](s32)
|
||||
; GREEDY-LABEL: name: smax_s32_ss_vgpr_use
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -131,9 +131,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; FAST: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY-LABEL: name: smax_s16_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
@ -141,9 +141,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s16) = G_TRUNC %0
|
||||
@ -167,9 +167,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; FAST: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; FAST: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GREEDY-LABEL: name: smax_s16_ss_vgpr_use
|
||||
@ -179,9 +179,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; GREEDY: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
|
||||
@ -13,13 +13,13 @@ body: |
|
||||
; FAST-LABEL: name: smin_s32_ss
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY-LABEL: name: smin_s32_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_SMIN %0, %1
|
||||
@ -101,14 +101,14 @@ body: |
|
||||
; FAST-LABEL: name: smin_s32_ss_vgpr_use
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; FAST: $vgpr0 = COPY [[SELECT]](s32)
|
||||
; GREEDY-LABEL: name: smin_s32_ss_vgpr_use
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -131,9 +131,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; FAST: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY-LABEL: name: smin_s16_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
@ -141,9 +141,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s16) = G_TRUNC %0
|
||||
@ -167,9 +167,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; FAST: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; FAST: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; FAST: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GREEDY-LABEL: name: smin_s16_ss_vgpr_use
|
||||
@ -179,9 +179,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[SEXT1:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[SEXT]], [[SEXT1]]
|
||||
; GREEDY: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; GREEDY: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
|
||||
@ -14,15 +14,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32)
|
||||
; GREEDY-LABEL: name: ssube_s32_sss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -43,18 +49,20 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
; GREEDY-LABEL: name: ssube_s32_vss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
@ -74,20 +82,18 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
; GREEDY-LABEL: name: ssube_s32_ssv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
@ -135,17 +141,17 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32)
|
||||
; GREEDY-LABEL: name: ssubee_s32_sss_noscc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
|
||||
@ -52,7 +52,7 @@ body: |
|
||||
liveins: $vgpr0_vgpr1
|
||||
; CHECK-LABEL: name: trunc_i64_to_i1_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s64)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s64)
|
||||
%0:_(s64) = COPY $vgpr0_vgpr1
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
...
|
||||
@ -80,7 +80,7 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: trunc_i32_to_i1_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
...
|
||||
|
||||
@ -13,15 +13,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||
; GREEDY-LABEL: name: uadde_s32_sss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -42,18 +48,20 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
; GREEDY-LABEL: name: uadde_s32_vss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
@ -73,20 +81,18 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
; GREEDY-LABEL: name: uadde_s32_ssv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
@ -134,17 +140,17 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||
; GREEDY-LABEL: name: uadde_s32_sss_noscc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
|
||||
@ -12,7 +12,8 @@ body: |
|
||||
; CHECK-LABEL: name: uaddo_s32_ss
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:scc(s1) = G_UADDO [[COPY]], [[COPY1]]
|
||||
; CHECK: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[COPY]], [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[UADDO1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
|
||||
|
||||
@ -13,13 +13,13 @@ body: |
|
||||
; FAST-LABEL: name: umax_s32_ss
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY-LABEL: name: umax_s32_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_UMAX %0, %1
|
||||
@ -101,14 +101,14 @@ body: |
|
||||
; FAST-LABEL: name: umax_s32_ss_vgpr_use
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; FAST: $vgpr0 = COPY [[SELECT]](s32)
|
||||
; GREEDY-LABEL: name: umax_s32_ss_vgpr_use
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -131,9 +131,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; FAST: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY-LABEL: name: umax_s16_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
@ -141,9 +141,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s16) = G_TRUNC %0
|
||||
@ -167,9 +167,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; FAST: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; FAST: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GREEDY-LABEL: name: umax_s16_ss_vgpr_use
|
||||
@ -179,9 +179,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ugt), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; GREEDY: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
|
||||
@ -13,13 +13,13 @@ body: |
|
||||
; FAST-LABEL: name: umin_s32_ss
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY-LABEL: name: umin_s32_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_UMIN %0, %1
|
||||
@ -101,14 +101,14 @@ body: |
|
||||
; FAST-LABEL: name: umin_s32_ss_vgpr_use
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; FAST: $vgpr0 = COPY [[SELECT]](s32)
|
||||
; GREEDY-LABEL: name: umin_s32_ss_vgpr_use
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[COPY]], [[COPY1]]
|
||||
; GREEDY: $vgpr0 = COPY [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
@ -131,9 +131,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; FAST: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY-LABEL: name: umin_s16_ss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
@ -141,9 +141,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %7(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s16) = G_TRUNC %0
|
||||
@ -167,9 +167,9 @@ body: |
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; FAST: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; FAST: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; FAST: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; FAST: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; FAST: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; GREEDY-LABEL: name: umin_s16_ss_vgpr_use
|
||||
@ -179,9 +179,9 @@ body: |
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
|
||||
; GREEDY: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; GREEDY: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC %8(s32)
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[ZEXT]](s32), [[ZEXT1]]
|
||||
; GREEDY: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s32), [[ZEXT]], [[ZEXT1]]
|
||||
; GREEDY: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC2]](s16)
|
||||
; GREEDY: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
|
||||
@ -14,15 +14,21 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s32) = G_USUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[USUBE1]](s32)
|
||||
; GREEDY-LABEL: name: usube_s32_sss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s32) = G_USUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[USUBE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
@ -43,18 +49,20 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
; GREEDY-LABEL: name: usube_s32_vss
|
||||
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $sgpr0
|
||||
@ -74,20 +82,18 @@ body: |
|
||||
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; FAST: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
; GREEDY-LABEL: name: usube_s32_ssv
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[TRUNC]]
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
@ -135,17 +141,17 @@ body: |
|
||||
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
|
||||
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
|
||||
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s32) = G_USUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[USUBE1]](s32)
|
||||
; GREEDY-LABEL: name: usube_s32_sss_noscc
|
||||
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
|
||||
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
||||
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; GREEDY: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:vcc(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
|
||||
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s32) = G_USUBE [[COPY]], [[COPY1]], [[ZEXT]]
|
||||
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[USUBE1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = COPY $sgpr2
|
||||
|
||||
@ -12,7 +12,8 @@ body: |
|
||||
; CHECK-LABEL: name: usubo_s32_ss
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[USUBO:%[0-9]+]]:sgpr(s32), [[USUBO1:%[0-9]+]]:scc(s1) = G_USUBO [[COPY]], [[COPY1]]
|
||||
; CHECK: [[USUBO:%[0-9]+]]:sgpr(s32), [[USUBO1:%[0-9]+]]:sgpr(s32) = G_USUBO [[COPY]], [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[USUBO1]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32), %3:_(s1) = G_USUBO %0, %1
|
||||
|
||||
@ -78,12 +78,15 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[COPY2]], [[COPY3]]
|
||||
; CHECK: S_NOP 0, implicit [[XOR]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s32) = G_CONSTANT i32 0
|
||||
@ -128,9 +131,10 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP1]]
|
||||
; CHECK: S_NOP 0, implicit [[XOR]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
@ -153,8 +157,11 @@ body: |
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK: S_NOP 0, implicit [[XOR]](s1)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -174,10 +181,13 @@ body: |
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[COPY2]]
|
||||
; CHECK: S_NOP 0, implicit [[XOR]](s1)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[ANYEXT]], [[ANYEXT1]]
|
||||
; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s1) = G_TRUNC [[XOR]](s32)
|
||||
; CHECK: S_NOP 0, implicit [[TRUNC2]](s1)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_TRUNC %0
|
||||
@ -734,3 +744,26 @@ body: |
|
||||
%1:_(<2 x s16>) = COPY $vgpr1
|
||||
%2:_(<2 x s16>) = G_XOR %0, %1
|
||||
...
|
||||
|
||||
---
|
||||
name: xor_i1_vcc_constant
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; CHECK-LABEL: name: xor_i1_vcc_constant
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[C1]](s1)
|
||||
; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[COPY1]]
|
||||
; CHECK: S_NOP 0, implicit [[XOR]](s1)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s32) = G_CONSTANT i32 0
|
||||
%2:_(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%3:_(s1) = G_CONSTANT i1 true
|
||||
%4:_(s1) = G_XOR %2, %3
|
||||
S_NOP 0, implicit %4
|
||||
...
|
||||
|
||||
@ -58,11 +58,12 @@ body: |
|
||||
; CHECK-LABEL: name: zext_s1_to_s16_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 15
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -79,10 +80,12 @@ body: |
|
||||
; CHECK-LABEL: name: zext_s1_to_s32_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -99,10 +102,12 @@ body: |
|
||||
; CHECK-LABEL: name: zext_s1_to_s64_scc
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1
|
||||
; CHECK: [[C1:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:sgpr(s64) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63
|
||||
; CHECK: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[LSHR:%[0-9]+]]:sgpr(s64) = G_LSHR [[SHL]], [[C]](s32)
|
||||
%0:_(s32) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(s1) = G_ICMP intpred(eq), %0, %1
|
||||
@ -238,11 +243,11 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: zext_s1_to_s16_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s16) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 15
|
||||
; CHECK: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[SHL]], [[C]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[SELECT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s16) = G_ZEXT %1
|
||||
@ -257,11 +262,10 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: zext_s1_to_s32_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31
|
||||
; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ANYEXT]], [[C]](s32)
|
||||
; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[SHL]], [[C]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s32) = G_ZEXT %1
|
||||
@ -276,10 +280,12 @@ body: |
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: zext_s1_to_s64_vgpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC]](s1)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[ZEXT]](s32), [[C]](s32)
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
|
||||
; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[C]], [[C1]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)
|
||||
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[COPY1]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s1) = G_TRUNC %0
|
||||
%2:_(s64) = G_ZEXT %1
|
||||
|
||||
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Reference in New Issue
Block a user