From 1a63466277c243194f797db91914fae2ab89a61a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 28 Jan 2021 16:08:47 -0800 Subject: [PATCH] [AArch64][GlobalISel] Enable CSE for the prelegalizer combiner. Differential Revision: https://reviews.llvm.org/D95647 --- .../AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 15 ++++++++++++--- .../combine-shift-immed-mismatch-crash.mir | 8 ++++---- .../GlobalISel/gisel-commandline-option.ll | 2 +- test/CodeGen/AArch64/O0-pipeline.ll | 2 +- 4 files changed, 18 insertions(+), 9 deletions(-) diff --git a/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp index a1cc0b42eb5..6e7fe7c9851 100644 --- a/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ b/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -205,6 +205,8 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreserved(); } + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -217,7 +219,13 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { if (MF.getProperties().hasProperty( MachineFunctionProperties::Property::FailedISel)) return false; - auto *TPC = &getAnalysis(); + auto &TPC = getAnalysis(); + + // Enable CSE. + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis().getCSEWrapper(); + auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig()); + const Function &F = MF.getFunction(); bool EnableOpt = MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F); @@ -226,8 +234,8 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { IsOptNone ? nullptr : &getAnalysis(); AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(), F.hasMinSize(), KB, MDT); - Combiner C(PCInfo, TPC); - return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr); + Combiner C(PCInfo, &TPC); + return C.combineMachineInstrs(MF, CSEInfo); } char AArch64PreLegalizerCombiner::ID = 0; @@ -236,6 +244,7 @@ INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE, false, false) INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis) +INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 machine instrs before legalization", false, false) diff --git a/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir b/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir index 481c71fbed6..0cfd974892c 100644 --- a/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir +++ b/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir @@ -11,16 +11,16 @@ body: | ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $x0 - ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF + ; CHECK: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9 - ; CHECK: [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF - ; CHECK: G_BRCOND [[DEF1]](s1), %bb.2 + ; CHECK: G_BRCOND [[DEF]](s1), %bb.2 ; CHECK: G_BR %bb.1 ; CHECK: bb.1: ; CHECK: successors: ; CHECK: bb.2: - ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4 from `i32* undef`, align 8) + ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p0) :: (load 4 from `i32* undef`, align 8) ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]] ; CHECK: [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]] ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 diff --git a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll index 48315532064..56c3926db26 100644 --- a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll +++ b/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll @@ -56,9 +56,9 @@ ; VERIFY-NEXT: Verify generated machine code ; ENABLED-NEXT: Analysis for ComputingKnownBits ; ENABLED-O1-NEXT: MachineDominator Tree Construction +; ENABLED-NEXT: Analysis containing CSE Info ; ENABLED-NEXT: PreLegalizerCombiner ; VERIFY-NEXT: Verify generated machine code -; ENABLED-NEXT: Analysis containing CSE Info ; ENABLED-NEXT: Legalizer ; VERIFY-NEXT: Verify generated machine code ; ENABLED: RegBankSelect diff --git a/test/CodeGen/AArch64/O0-pipeline.ll b/test/CodeGen/AArch64/O0-pipeline.ll index 7d2caec7f3c..6d4ca758275 100644 --- a/test/CodeGen/AArch64/O0-pipeline.ll +++ b/test/CodeGen/AArch64/O0-pipeline.ll @@ -34,8 +34,8 @@ ; CHECK-NEXT: Analysis containing CSE Info ; CHECK-NEXT: IRTranslator ; CHECK-NEXT: Analysis for ComputingKnownBits -; CHECK-NEXT: AArch64PreLegalizerCombiner ; CHECK-NEXT: Analysis containing CSE Info +; CHECK-NEXT: AArch64PreLegalizerCombiner ; CHECK-NEXT: Legalizer ; CHECK-NEXT: AArch64PostLegalizerLowering ; CHECK-NEXT: RegBankSelect