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Fix ubsan error in tblgen with signed left shift

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UBSAN complains when tblgen performs SHL of a negative
value.

Differential Revision: https://reviews.llvm.org/D81952
This commit is contained in:
Stanislav Mekhanoshin 2020-06-16 10:21:09 -07:00
parent b2733d94ae
commit 1a6d6ebda9
2 changed files with 2 additions and 2 deletions
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2
lib/TableGen/Record.cpp
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@ -1030,7 +1030,7 @@ Init *BinOpInit::Fold(Record *CurRec) const {
case MUL: Result = LHSv * RHSv; break;
case AND: Result = LHSv & RHSv; break;
case OR: Result = LHSv | RHSv; break;
case SHL: Result = LHSv << RHSv; break;
case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
case SRA: Result = LHSv >> RHSv; break;
case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
}

2
lib/Target/AMDGPU/SMInstructions.td
View File

@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {
def : GCNPat <
(i64 (readcyclecounter)),
(REG_SEQUENCE SReg_64,
(S_GETREG_B32 -26595), sub0,
(S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
(S_MOV_B32 (i32 0)), sub1)
>;
} // let OtherPredicates = [HasNoSMemTimeInst]