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[Hexagon] Guard the generation of lookup table
The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306869
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@ -49,6 +49,10 @@ static cl::opt<bool> TraceGVPlacement("trace-gv-placement",
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cl::Hidden, cl::init(false),
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cl::desc("Trace global value placement"));
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static cl::opt<bool>
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EmitJtInText("hexagon-emit-jt-text", cl::Hidden, cl::init(false),
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cl::desc("Emit hexagon jump tables in function section"));
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// TraceGVPlacement controls messages for all builds. For builds with assertions
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// (debug or release), messages are also controlled by the usual debug flags
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// (e.g. -debug and -debug-only=globallayout)
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@ -256,6 +260,11 @@ unsigned HexagonTargetObjectFile::getSmallDataSize() const {
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return SmallDataThreshold;
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}
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bool HexagonTargetObjectFile::shouldPutJumpTableInFunctionSection(
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bool UsesLabelDifference, const Function &F) const {
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return EmitJtInText;
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}
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/// Descends any type down to "elementary" components,
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/// discovering the smallest addressable one.
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/// If zero is returned, declaration will not be modified.
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@ -33,6 +33,9 @@ namespace llvm {
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unsigned getSmallDataSize() const;
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bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference,
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const Function &F) const override;
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private:
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MCSectionELF *SmallDataSection;
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MCSectionELF *SmallBSSSection;
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57
test/CodeGen/Hexagon/jt-in-text.ll
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57
test/CodeGen/Hexagon/jt-in-text.ll
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@ -0,0 +1,57 @@
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; RUN: llc -hexagon-emit-jt-text=true < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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; CHECK: .text
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; CHECK-NOT: .rodata
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; CHECK: .word
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@lane0_pwr_st = global i32 0, align 4
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@lane1_pwr_st = global i32 0, align 4
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@lane2_pwr_st = global i32 0, align 4
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@lane3_pwr_st = global i32 0, align 4
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; Function Attrs: noinline nounwind
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define void @test2(i32 %lane_id, i32 %rx_pwr_st) #0 {
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entry:
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%lane_id.addr = alloca i32, align 4
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%rx_pwr_st.addr = alloca i32, align 4
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store i32 %lane_id, i32* %lane_id.addr, align 4
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store i32 %rx_pwr_st, i32* %rx_pwr_st.addr, align 4
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%0 = load i32, i32* %lane_id.addr, align 4
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switch i32 %0, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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i32 15, label %sw.bb4
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]
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sw.bb: ; preds = %entry
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store i32 1, i32* @lane0_pwr_st, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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store i32 1, i32* @lane1_pwr_st, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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store i32 1, i32* @lane2_pwr_st, align 4
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br label %sw.epilog
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sw.bb3: ; preds = %entry
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store i32 1, i32* @lane3_pwr_st, align 4
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br label %sw.epilog
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sw.bb4: ; preds = %entry
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store i32 1, i32* @lane0_pwr_st, align 4
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store i32 1, i32* @lane1_pwr_st, align 4
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store i32 1, i32* @lane2_pwr_st, align 4
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store i32 1, i32* @lane3_pwr_st, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
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ret void
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}
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attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
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