mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
[AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.
llvm-svn: 268891
This commit is contained in:
Craig Topper
parent
5bcf351ca9
commit
1a7c59b5bb
@ -5543,13 +5543,13 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_avx512_mask_cvtsd2ss_round :
|
||||
GCCBuiltin<"__builtin_ia32_cvtsd2ss_round_mask">,
|
||||
Intrinsic<[llvm_v4f32_ty],
|
||||
[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[llvm_v4f32_ty, llvm_v2f64_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtss2sd_round :
|
||||
GCCBuiltin<"__builtin_ia32_cvtss2sd_round_mask">,
|
||||
Intrinsic<[llvm_v2f64_ty],
|
||||
[ llvm_v4f32_ty, llvm_v4f32_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[llvm_v2f64_ty, llvm_v4f32_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtpd2ps :
|
||||
|
||||
@ -5097,15 +5097,15 @@ let Predicates = [HasAVX512] in {
|
||||
multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
|
||||
X86VectorVTInfo _Src, SDNode OpNode> {
|
||||
defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
|
||||
(ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(_.VT (OpNode (_Src.VT _Src.RC:$src1),
|
||||
(_.VT (OpNode (_.VT _.RC:$src1),
|
||||
(_Src.VT _Src.RC:$src2)))>,
|
||||
EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
|
||||
defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(_.VT (OpNode (_Src.VT _Src.RC:$src1),
|
||||
(_.VT (OpNode (_.VT _.RC:$src1),
|
||||
(_Src.VT (scalar_to_vector
|
||||
(_Src.ScalarLdFrag addr:$src2)))))>,
|
||||
EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
|
||||
@ -5115,9 +5115,9 @@ multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _
|
||||
multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
|
||||
X86VectorVTInfo _Src, SDNode OpNodeRnd> {
|
||||
defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
|
||||
(ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
|
||||
"{sae}, $src2, $src1", "$src1, $src2, {sae}",
|
||||
(_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
|
||||
(_.VT (OpNodeRnd (_.VT _.RC:$src1),
|
||||
(_Src.VT _Src.RC:$src2),
|
||||
(i32 FROUND_NO_EXC)))>,
|
||||
EVEX_4V, VEX_LIG, EVEX_B;
|
||||
@ -5127,9 +5127,9 @@ multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTIn
|
||||
multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
|
||||
X86VectorVTInfo _Src, SDNode OpNodeRnd> {
|
||||
defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
|
||||
(ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
|
||||
"$rc, $src2, $src1", "$src1, $src2, $rc",
|
||||
(_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
|
||||
(_.VT (OpNodeRnd (_.VT _.RC:$src1),
|
||||
(_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
|
||||
EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
|
||||
EVEX_B, EVEX_RC;
|
||||
|
||||
@ -149,32 +149,32 @@ def X86vfpround: SDNode<"X86ISD::VFPROUND",
|
||||
SDTCisOpSmallerThanOp<0, 1>]>>;
|
||||
|
||||
def X86fround: SDNode<"X86ISD::VFPROUND",
|
||||
SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
|
||||
SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, f64>,
|
||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCVecEltisVT<2, f64>,
|
||||
SDTCisOpSmallerThanOp<0, 1>]>>;
|
||||
SDTCisSameSizeAs<0, 2>,
|
||||
SDTCisOpSmallerThanOp<0, 2>]>>;
|
||||
def X86froundRnd: SDNode<"X86ISD::VFPROUND",
|
||||
SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
|
||||
SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, f64>,
|
||||
SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCVecEltisVT<2, f64>,
|
||||
SDTCisOpSmallerThanOp<0, 1>,
|
||||
SDTCisSameSizeAs<0, 2>,
|
||||
SDTCisOpSmallerThanOp<0, 2>,
|
||||
SDTCisInt<3>]>>;
|
||||
|
||||
def X86fpext : SDNode<"X86ISD::VFPEXT",
|
||||
SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
|
||||
SDTCVecEltisVT<0, f64>,
|
||||
SDTCVecEltisVT<1, f32>,
|
||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCVecEltisVT<2, f32>,
|
||||
SDTCisOpSmallerThanOp<1, 0>]>>;
|
||||
SDTCisSameSizeAs<0, 2>,
|
||||
SDTCisOpSmallerThanOp<2, 0>]>>;
|
||||
|
||||
def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
|
||||
SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
|
||||
SDTCVecEltisVT<0, f64>,
|
||||
SDTCVecEltisVT<1, f32>,
|
||||
SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
|
||||
SDTCisSameAs<0, 1>,
|
||||
SDTCVecEltisVT<2, f32>,
|
||||
SDTCisOpSmallerThanOp<1, 0>,
|
||||
SDTCisSameSizeAs<0, 2>,
|
||||
SDTCisOpSmallerThanOp<2, 0>,
|
||||
SDTCisInt<3>]>>;
|
||||
|
||||
def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
|
||||
|
||||
@ -6142,9 +6142,9 @@ define <8 x i64>@test_int_x86_avx512_mask_inserti64x4_512(<8 x i64> %x0, <4 x i6
|
||||
ret <8 x i64> %res4
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<4 x float>, <4 x float>, <2 x double>, i8, i32)
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double>, <4 x float>, <2 x double>, i8, i32)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<4 x float> %x0,<4 x float> %x1, <2 x double> %x2, i8 %x3) {
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<2 x double> %x0,<4 x float> %x1, <2 x double> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ss2sd_round:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: andl $1, %edi
|
||||
@ -6153,15 +6153,15 @@ define <2 x double>@test_int_x86_avx512_mask_cvt_ss2sd_round(<4 x float> %x0,<4
|
||||
; CHECK-NEXT: vcvtss2sd {sae}, %xmm1, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<4 x float> %x0, <4 x float> %x1, <2 x double> %x2, i8 %x3, i32 4)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<4 x float> %x0, <4 x float> %x1, <2 x double> %x2, i8 -1, i32 8)
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 %x3, i32 4)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtss2sd.round(<2 x double> %x0, <4 x float> %x1, <2 x double> %x2, i8 -1, i32 8)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<2 x double>, <2 x double>, <4 x float>, i8, i32)
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float>, <2 x double>, <4 x float>, i8, i32)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<2 x double> %x0,<2 x double> %x1, <4 x float> %x2, i8 %x3) {
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<4 x float> %x0,<2 x double> %x1, <4 x float> %x2, i8 %x3) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_sd2ss_round:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: andl $1, %edi
|
||||
@ -6170,8 +6170,8 @@ define <4 x float>@test_int_x86_avx512_mask_cvt_sd2ss_round(<2 x double> %x0,<2
|
||||
; CHECK-NEXT: vcvtsd2ss {rn-sae}, %xmm1, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<2 x double> %x0, <2 x double> %x1, <4 x float> %x2, i8 %x3, i32 3)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<2 x double> %x0, <2 x double> %x1, <4 x float> %x2, i8 -1, i32 8)
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 %x3, i32 3)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtsd2ss.round(<4 x float> %x0, <2 x double> %x1, <4 x float> %x2, i8 -1, i32 8)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user