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Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens!

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llvm-svn: 53932
This commit is contained in:
Evan Cheng 2008-07-22 20:42:56 +00:00
parent b7d67aaa88
commit 1aa928a8e6
2 changed files with 18 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4953,7 +4953,8 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
// look though conversions that change things like v4f32 to v2f64.
if (V->getOpcode() == ISD::BIT_CONVERT) {
SDOperand ConvInput = V->getOperand(0);
if (ConvInput.getValueType().getVectorNumElements() == NumElts)
if (ConvInput.getValueType().isVector() &&
ConvInput.getValueType().getVectorNumElements() == NumElts)
V = ConvInput.Val;
}

16
test/CodeGen/X86/2008-07-22-CombinerCrash.ll Normal file
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@ -0,0 +1,16 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
; PR2566
external global i16 ; <i16*>:0 [#uses=1]
external global <4 x i16> ; <<4 x i16>*>:1 [#uses=1]
declare void @abort()
define void @t() nounwind {
load i16* @0 ; <i16>:1 [#uses=1]
zext i16 %1 to i64 ; <i64>:2 [#uses=1]
bitcast i64 %2 to <4 x i16> ; <<4 x i16>>:3 [#uses=1]
shufflevector <4 x i16> %3, <4 x i16> undef, <4 x i32> zeroinitializer ; <<4 x i16>>:4 [#uses=1]
store <4 x i16> %4, <4 x i16>* @1
ret void
}