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https://github.com/RPCS3/llvm-mirror.git
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[X86] Generalize and combine some similar type constraints and node types. No changes to the isel table size so the separation wasn't buying us anything.
llvm-svn: 270026
This commit is contained in:
Craig Topper
parent
c298b9dab5
commit
1aff453749
@ -4963,28 +4963,28 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT ,
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// Convert float/double to signed/unsigned int 32/64
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
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X86cvtss2si, "cvtss2si">,
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X86cvts2si, "cvtss2si">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
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X86cvtss2si, "cvtss2si">,
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X86cvts2si, "cvtss2si">,
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XS, VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
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X86cvtss2usi, "cvtss2usi">,
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X86cvts2usi, "cvtss2usi">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
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X86cvtss2usi, "cvtss2usi">, XS, VEX_W,
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X86cvts2usi, "cvtss2usi">, XS, VEX_W,
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EVEX_CD8<32, CD8VT1>;
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
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X86cvtsd2si, "cvtsd2si">,
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X86cvts2si, "cvtsd2si">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
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X86cvtsd2si, "cvtsd2si">,
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X86cvts2si, "cvtsd2si">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
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X86cvtsd2usi, "cvtsd2usi">,
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X86cvts2usi, "cvtsd2usi">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
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X86cvtsd2usi, "cvtsd2usi">, XD, VEX_W,
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X86cvts2usi, "cvtsd2usi">, XD, VEX_W,
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EVEX_CD8<64, CD8VT1>;
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// The SSE version of these instructions are disabled for AVX512.
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@ -5038,11 +5038,11 @@ let Predicates = [HasAVX512] in {
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let isCodeGenOnly = 1,hasSideEffects = 0 in {
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def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
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[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
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(i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
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def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
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!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
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[(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
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[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
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(i32 FROUND_NO_EXC)))]>,
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EVEX,VEX_LIG , EVEX_B;
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let mayLoad = 1 in
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@ -5057,29 +5057,29 @@ let Predicates = [HasAVX512] in {
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defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
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fp_to_sint,X86cvttss2IntRnd>,
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fp_to_sint,X86cvtts2IntRnd>,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
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fp_to_sint,X86cvttss2IntRnd>,
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fp_to_sint,X86cvtts2IntRnd>,
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VEX_W, XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
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fp_to_sint,X86cvttsd2IntRnd>,
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fp_to_sint,X86cvtts2IntRnd>,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
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fp_to_sint,X86cvttsd2IntRnd>,
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fp_to_sint,X86cvtts2IntRnd>,
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VEX_W, XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
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fp_to_uint,X86cvttss2UIntRnd>,
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fp_to_uint,X86cvtts2UIntRnd>,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
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fp_to_uint,X86cvttss2UIntRnd>,
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fp_to_uint,X86cvtts2UIntRnd>,
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XS,VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
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fp_to_uint,X86cvttsd2UIntRnd>,
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fp_to_uint,X86cvtts2UIntRnd>,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
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fp_to_uint,X86cvttsd2UIntRnd>,
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fp_to_uint,X86cvtts2UIntRnd>,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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let Predicates = [HasAVX512] in {
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def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
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@ -5509,59 +5509,59 @@ defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
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X86VUintToFpRnd>, XD,
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EVEX_CD8<32, CD8VF>;
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defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
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X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
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defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int,
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X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
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defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
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X86cvtpd2IntRnd>, XD, VEX_W,
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defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int,
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X86cvtp2IntRnd>, XD, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
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X86cvtps2UIntRnd>,
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defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt,
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X86cvtp2UIntRnd>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
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X86cvtpd2UIntRnd>, VEX_W,
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defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt,
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X86cvtp2UIntRnd>, VEX_W,
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PS, EVEX_CD8<64, CD8VF>;
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defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
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X86cvtpd2IntRnd>, VEX_W,
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defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int,
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X86cvtp2IntRnd>, VEX_W,
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PD, EVEX_CD8<64, CD8VF>;
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defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
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X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int,
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X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
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X86cvtpd2UIntRnd>, VEX_W,
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defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt,
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X86cvtp2UIntRnd>, VEX_W,
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PD, EVEX_CD8<64, CD8VF>;
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defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
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X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt,
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X86cvtp2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
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X86VFpToSlongRnd>, VEX_W,
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X86VFpToSintRnd>, VEX_W,
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PD, EVEX_CD8<64, CD8VF>;
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defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
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X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
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X86VFpToSintRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
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X86VFpToUlongRnd>, VEX_W,
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X86VFpToUintRnd>, VEX_W,
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PD, EVEX_CD8<64, CD8VF>;
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defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
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X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
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X86VFpToUintRnd>, PD, EVEX_CD8<32, CD8VH>;
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defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
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X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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X86VSintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
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X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
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X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
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X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
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defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
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X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
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X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
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let Predicates = [HasAVX512, NoVLX] in {
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def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
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@ -513,75 +513,44 @@ def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
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SDTCisSameAs<0,1>, SDTCisInt<2>,
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SDTCisVT<3, i32>]>;
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def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
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def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
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SDTCisInt<0>, SDTCisFP<1>]>;
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def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCVecEltisVT<1, f64>,
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SDTCisVT<2, i32>]>;
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def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
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SDTCVecEltisVT<1, f64>,
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SDTCisVT<2, i32>]>;
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def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCVecEltisVT<1, f32>,
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SDTCisVT<2, i32>]>;
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SDTCisInt<0>, SDTCisFP<1>,
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SDTCisVT<2, i32>]>;
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def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
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SDTCVecEltisVT<1, f32>,
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SDTCisVT<2, i32>]>;
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SDTCisVec<1>, SDTCisVT<2, i32>]>;
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def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
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SDTCisVT<2, i32>]>;
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def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
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SDTCisVT<2, i32>]>;
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def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
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SDTCisVT<2, i32>]>;
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def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
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SDTCisFP<0>, SDTCisInt<1>,
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SDTCisVT<2, i32>]>;
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// Scalar
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def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
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def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
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def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
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def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
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def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtts2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
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def X86cvtts2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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def X86cvtsd2si : SDNode<"X86ISD::SCALAR_FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtsd2usi : SDNode<"X86ISD::SCALAR_FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtss2si : SDNode<"X86ISD::SCALAR_FP_TO_SINT_RND", SDTSFloatToIntRnd>;
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def X86cvtss2usi : SDNode<"X86ISD::SCALAR_FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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def X86cvts2si : SDNode<"X86ISD::SCALAR_FP_TO_SINT_RND", SDTSFloatToIntRnd>;
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def X86cvts2usi : SDNode<"X86ISD::SCALAR_FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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// Vector with rounding mode
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// cvtt fp-to-int staff
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def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
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def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
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def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
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def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
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def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTFloatToIntRnd>;
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def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTFloatToIntRnd>;
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def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
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def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
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def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
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def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
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// cvt fp-to-int staff
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def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
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def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
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def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
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def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
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def X86cvtp2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
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def X86cvtp2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
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// Vector without rounding mode
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def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
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def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
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def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
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def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
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def X86cvtp2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
|
||||
def X86cvtp2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
|
||||
|
||||
def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
|
||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user