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[WebAssemby] Enforce FIFO ordering for instructions using stackified registers.
llvm-svn: 253634
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e196b98966
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@ -58,6 +58,18 @@ FunctionPass *llvm::createWebAssemblyRegStackify() {
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return new WebAssemblyRegStackify();
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}
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// Decorate the given instruction with implicit operands that enforce the
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// expression stack ordering constraints.
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static void ImposeStackOrdering(MachineInstr *MI) {
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// Read and write the opaque EXPR_STACK register.
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/true,
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/*isImp=*/true));
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MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
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/*isDef=*/false,
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/*isImp=*/true));
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}
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bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** Register Stackifying **********\n"
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"********** Function: "
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@ -80,6 +92,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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// Iterate through the inputs in reverse order, since we'll be pulling
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// operands off the stack in FIFO order.
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bool AnyStackified = false;
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for (MachineOperand &Op : reverse(Insert->uses())) {
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// We're only interested in explicit virtual register operands.
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if (!Op.isReg() || Op.isImplicit())
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@ -128,11 +141,13 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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continue;
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Changed = true;
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AnyStackified = true;
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if (OneUse) {
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// Move the def down and nest it in the current instruction.
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MBB.insert(MachineBasicBlock::instr_iterator(Insert),
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Def->removeFromParent());
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MFI.stackifyVReg(Reg);
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ImposeStackOrdering(Def);
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Insert = Def;
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} else {
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// Clone the def down and nest it in the current instruction.
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@ -145,11 +160,22 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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Clone->getOperand(0).setReg(NewReg);
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MBB.insert(MachineBasicBlock::instr_iterator(Insert), Clone);
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MFI.stackifyVReg(Reg);
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ImposeStackOrdering(Clone);
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Insert = Clone;
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}
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}
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if (AnyStackified)
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ImposeStackOrdering(&MI);
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}
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}
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// If we used EXPR_STACK anywhere, add it to the live-in sets everywhere
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// so that it never looks like a use-before-def.
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if (Changed) {
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MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
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for (MachineBasicBlock &MBB : MF)
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MBB.addLiveIn(WebAssembly::EXPR_STACK);
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}
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return Changed;
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}
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@ -39,6 +39,10 @@ def SP64 : WebAssemblyReg<"%SP64">;
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def F32_0 : WebAssemblyReg<"%f32.0">;
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def F64_0 : WebAssemblyReg<"%f64.0">;
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// The expression stack "register". This is an opaque entity which serves to
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// order uses and defs that must remain in FIFO order.
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def EXPR_STACK : WebAssemblyReg<"STACK">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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