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R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change them all to be consistently lowercase. Now, non-encoding fields and convenience bits are capitalized. Also remove weird looking empty line in some of the formats. llvm-svn: 229613
This commit is contained in:
Matt Arsenault
parent
4a131e829b
commit
1b741feef5
@ -74,13 +74,11 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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}
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class Enc32 {
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field bits<32> Inst;
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int Size = 4;
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}
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class Enc64 {
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field bits<64> Inst;
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int Size = 8;
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}
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@ -139,53 +137,48 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
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//===----------------------------------------------------------------------===//
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class SOP1e <bits<8> op> : Enc32 {
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bits<7> sdst;
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bits<8> ssrc0;
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bits<7> SDST;
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bits<8> SSRC0;
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let Inst{7-0} = SSRC0;
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let Inst{7-0} = ssrc0;
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let Inst{15-8} = op;
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let Inst{22-16} = SDST;
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let Inst{22-16} = sdst;
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let Inst{31-23} = 0x17d; //encoding;
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}
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class SOP2e <bits<7> op> : Enc32 {
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bits<7> sdst;
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bits<8> ssrc0;
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bits<8> ssrc1;
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bits<7> SDST;
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = SDST;
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let Inst{7-0} = ssrc0;
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let Inst{15-8} = ssrc1;
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let Inst{22-16} = sdst;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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}
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class SOPCe <bits<7> op> : Enc32 {
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bits<8> ssrc0;
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bits<8> ssrc1;
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{7-0} = ssrc0;
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let Inst{15-8} = ssrc1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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}
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class SOPKe <bits<5> op> : Enc32 {
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bits <7> sdst;
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bits <16> simm16;
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bits <7> SDST;
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = SDST;
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let Inst{15-0} = simm16;
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let Inst{22-16} = sdst;
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let Inst{27-23} = op;
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let Inst{31-28} = 0xb; //encoding
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}
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class SOPPe <bits<7> op> : Enc32 {
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bits <16> simm16;
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let Inst{15-0} = simm16;
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@ -194,15 +187,14 @@ class SOPPe <bits<7> op> : Enc32 {
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}
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class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
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bits<7> sdst;
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bits<7> sbase;
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bits<8> offset;
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bits<7> SDST;
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bits<7> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{7-0} = offset;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE{6-1};
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let Inst{21-15} = SDST;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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}
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@ -286,31 +278,28 @@ class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
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//===----------------------------------------------------------------------===//
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class VOP1e <bits<8> op> : Enc32 {
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bits<8> vdst;
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bits<9> src0;
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bits<8> VDST;
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bits<9> SRC0;
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let Inst{8-0} = SRC0;
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let Inst{8-0} = src0;
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let Inst{16-9} = op;
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let Inst{24-17} = VDST;
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let Inst{24-17} = vdst;
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let Inst{31-25} = 0x3f; //encoding
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}
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class VOP2e <bits<6> op> : Enc32 {
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bits<8> vdst;
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bits<9> src0;
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bits<8> vsrc1;
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bits<8> VDST;
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = VDST;
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let Inst{8-0} = src0;
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let Inst{16-9} = vsrc1;
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let Inst{24-17} = vdst;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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}
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class VOP3e <bits<9> op> : Enc64 {
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bits<8> dst;
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bits<2> src0_modifiers;
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bits<9> src0;
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@ -338,7 +327,6 @@ class VOP3e <bits<9> op> : Enc64 {
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}
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class VOP3be <bits<9> op> : Enc64 {
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bits<8> vdst;
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bits<2> src0_modifiers;
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bits<9> src0;
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@ -363,33 +351,30 @@ class VOP3be <bits<9> op> : Enc64 {
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}
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class VOPCe <bits<8> op> : Enc32 {
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bits<9> src0;
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bits<8> vsrc1;
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{8-0} = src0;
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let Inst{16-9} = vsrc1;
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e;
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}
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class VINTRPe <bits<2> op> : Enc32 {
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bits<8> vdst;
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bits<8> vsrc;
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bits<2> attrchan;
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bits<6> attr;
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bits<8> VDST;
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bits<8> VSRC;
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bits<2> ATTRCHAN;
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bits<6> ATTR;
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let Inst{7-0} = VSRC;
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let Inst{9-8} = ATTRCHAN;
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let Inst{15-10} = ATTR;
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let Inst{7-0} = vsrc;
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let Inst{9-8} = attrchan;
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let Inst{15-10} = attr;
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let Inst{17-16} = op;
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let Inst{25-18} = VDST;
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let Inst{25-18} = vdst;
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let Inst{31-26} = 0x32; // encoding
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}
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class DSe <bits<8> op> : Enc64 {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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@ -410,7 +395,6 @@ class DSe <bits<8> op> : Enc64 {
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}
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class MUBUFe <bits<7> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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@ -441,67 +425,65 @@ class MUBUFe <bits<7> op> : Enc64 {
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}
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class MTBUFe <bits<3> op> : Enc64 {
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bits<8> vdata;
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<1> addr64;
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bits<4> dfmt;
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bits<3> nfmt;
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bits<8> vaddr;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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bits<8> VDATA;
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bits<12> OFFSET;
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bits<1> OFFEN;
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bits<1> IDXEN;
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bits<1> GLC;
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bits<1> ADDR64;
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bits<4> DFMT;
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bits<3> NFMT;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<1> SLC;
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bits<1> TFE;
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bits<8> SOFFSET;
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let Inst{11-0} = OFFSET;
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let Inst{12} = OFFEN;
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let Inst{13} = IDXEN;
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let Inst{14} = GLC;
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let Inst{15} = ADDR64;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{15} = addr64;
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let Inst{18-16} = op;
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let Inst{22-19} = DFMT;
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let Inst{25-23} = NFMT;
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let Inst{22-19} = dfmt;
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let Inst{25-23} = nfmt;
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{54} = slc;
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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}
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class MIMGe <bits<7> op> : Enc64 {
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bits<8> vdata;
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bits<4> dmask;
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bits<1> unorm;
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bits<1> glc;
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bits<1> da;
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bits<1> r128;
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bits<1> tfe;
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bits<1> lwe;
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bits<1> slc;
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bits<8> vaddr;
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bits<7> srsrc;
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bits<7> ssamp;
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bits<8> VDATA;
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bits<4> DMASK;
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bits<1> UNORM;
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bits<1> GLC;
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bits<1> DA;
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bits<1> R128;
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bits<1> TFE;
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bits<1> LWE;
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bits<1> SLC;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<7> SSAMP;
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let Inst{11-8} = DMASK;
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let Inst{12} = UNORM;
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let Inst{13} = GLC;
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let Inst{14} = DA;
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let Inst{15} = R128;
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let Inst{16} = TFE;
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let Inst{17} = LWE;
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let Inst{11-8} = dmask;
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let Inst{12} = unorm;
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let Inst{13} = glc;
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let Inst{14} = da;
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let Inst{15} = r128;
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let Inst{16} = tfe;
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let Inst{17} = lwe;
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let Inst{24-18} = op;
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let Inst{25} = SLC;
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let Inst{25} = slc;
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let Inst{31-26} = 0x3c;
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{57-53} = SSAMP{6-2};
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{57-53} = ssamp{6-2};
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}
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class FLATe<bits<7> op> : Enc64 {
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@ -525,26 +507,26 @@ class FLATe<bits<7> op> : Enc64 {
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}
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class EXPe : Enc64 {
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bits<4> EN;
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bits<6> TGT;
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bits<1> COMPR;
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bits<1> DONE;
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bits<1> VM;
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bits<8> VSRC0;
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bits<8> VSRC1;
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bits<8> VSRC2;
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bits<8> VSRC3;
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bits<4> en;
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bits<6> tgt;
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bits<1> compr;
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bits<1> done;
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bits<1> vm;
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bits<8> vsrc0;
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bits<8> vsrc1;
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bits<8> vsrc2;
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bits<8> vsrc3;
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let Inst{3-0} = EN;
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let Inst{9-4} = TGT;
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let Inst{10} = COMPR;
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let Inst{11} = DONE;
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let Inst{12} = VM;
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let Inst{3-0} = en;
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let Inst{9-4} = tgt;
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let Inst{10} = compr;
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let Inst{11} = done;
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let Inst{12} = vm;
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let Inst{31-26} = 0x3e;
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let Inst{39-32} = VSRC0;
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let Inst{47-40} = VSRC1;
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let Inst{55-48} = VSRC2;
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let Inst{63-56} = VSRC3;
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let Inst{39-32} = vsrc0;
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let Inst{47-40} = vsrc1;
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let Inst{55-48} = vsrc2;
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let Inst{63-56} = vsrc3;
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}
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let Uses = [EXEC] in {
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@ -419,12 +419,12 @@ multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
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def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
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opName#" $dst"> {
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let SSRC0 = 0;
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let ssrc0 = 0;
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}
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def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
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opName#" $dst"> {
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let SSRC0 = 0;
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let ssrc0 = 0;
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}
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}
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@ -1986,7 +1986,7 @@ class MIMG_NoSampler_Helper <bits<7> op, string asm,
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc",
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[]> {
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let SSAMP = 0;
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let ssamp = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let hasPostISelHook = 1;
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@ -12,7 +12,6 @@
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//===----------------------------------------------------------------------===//
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class DSe_vi <bits<8> op> : Enc64 {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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@ -33,7 +32,6 @@ class DSe_vi <bits<8> op> : Enc64 {
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}
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class MUBUFe_vi <bits<7> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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@ -62,7 +60,6 @@ class MUBUFe_vi <bits<7> op> : Enc64 {
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}
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class MTBUFe_vi <bits<4> op> : Enc64 {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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@ -93,7 +90,6 @@ class MTBUFe_vi <bits<4> op> : Enc64 {
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}
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class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
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bits<7> sbase;
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bits<7> sdata;
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bits<1> glc;
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@ -109,7 +105,6 @@ class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
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}
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class VOP3e_vi <bits<10> op> : Enc64 {
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bits<8> dst;
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bits<2> src0_modifiers;
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bits<9> src0;
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