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[X86][AVX512] Cleanup bit logic scheduler classes
llvm-svn: 319767
This commit is contained in:
Simon Pilgrim
parent
3ff1bb935a
commit
1b86bca5d7
@ -4597,7 +4597,7 @@ let Predicates = [HasAVX512] in {
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// be set to null_frag for 32-bit elements.
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multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode,
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SDNode OpNodeMsk, X86VectorVTInfo _,
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SDNode OpNodeMsk, OpndItins itins, X86VectorVTInfo _,
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bit IsCommutable = 0> {
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let hasSideEffects = 0 in
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defm rr : AVX512_maskable_logic<opc, MRMSrcReg, _, (outs _.RC:$dst),
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@ -4607,8 +4607,8 @@ multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr,
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(bitconvert (_.VT _.RC:$src2)))),
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(_.VT (bitconvert (_.i64VT (OpNodeMsk _.RC:$src1,
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_.RC:$src2)))),
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IIC_SSE_BIT_P_RR, IsCommutable>,
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AVX512BIBase, EVEX_4V;
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itins.rr, IsCommutable>, AVX512BIBase, EVEX_4V,
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Sched<[itins.Sched]>;
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let hasSideEffects = 0, mayLoad = 1 in
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defm rm : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
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@ -4618,17 +4618,18 @@ multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr,
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(bitconvert (_.LdFrag addr:$src2)))),
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(_.VT (bitconvert (_.i64VT (OpNodeMsk _.RC:$src1,
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(bitconvert (_.LdFrag addr:$src2)))))),
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IIC_SSE_BIT_P_RM>,
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AVX512BIBase, EVEX_4V;
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itins.rm>, AVX512BIBase, EVEX_4V,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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// OpNodeMsk is the OpNode to use where element size is important. So use
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// for all of the broadcast patterns.
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multiclass avx512_logic_rmb<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode,
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SDNode OpNodeMsk, X86VectorVTInfo _,
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SDNode OpNodeMsk, OpndItins itins, X86VectorVTInfo _,
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bit IsCommutable = 0> :
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avx512_logic_rm<opc, OpcodeStr, OpNode, OpNodeMsk, _, IsCommutable> {
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avx512_logic_rm<opc, OpcodeStr, OpNode, OpNodeMsk, itins, _,
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IsCommutable> {
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defm rmb : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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"${src2}"##_.BroadcastStr##", $src1",
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@ -4641,40 +4642,42 @@ multiclass avx512_logic_rmb<bits<8> opc, string OpcodeStr,
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(bitconvert
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))))))),
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IIC_SSE_BIT_P_RM>,
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AVX512BIBase, EVEX_4V, EVEX_B;
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itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass avx512_logic_rmb_vl<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode,
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SDNode OpNodeMsk, AVX512VLVectorVTInfo VTInfo,
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SDNode OpNodeMsk, OpndItins itins,
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AVX512VLVectorVTInfo VTInfo,
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bit IsCommutable = 0> {
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let Predicates = [HasAVX512] in
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defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, VTInfo.info512,
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IsCommutable>, EVEX_V512;
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defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
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VTInfo.info512, IsCommutable>, EVEX_V512;
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk,
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defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
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VTInfo.info256, IsCommutable>, EVEX_V256;
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defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk,
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defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, OpNodeMsk, itins,
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VTInfo.info128, IsCommutable>, EVEX_V128;
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}
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}
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multiclass avx512_logic_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
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SDNode OpNode, bit IsCommutable = 0> {
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defm Q : avx512_logic_rmb_vl<opc_q, OpcodeStr#"q", OpNode, OpNode,
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SDNode OpNode, OpndItins itins,
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bit IsCommutable = 0> {
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defm Q : avx512_logic_rmb_vl<opc_q, OpcodeStr#"q", OpNode, OpNode, itins,
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avx512vl_i64_info, IsCommutable>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm D : avx512_logic_rmb_vl<opc_d, OpcodeStr#"d", null_frag, OpNode,
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defm D : avx512_logic_rmb_vl<opc_d, OpcodeStr#"d", null_frag, OpNode, itins,
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avx512vl_i32_info, IsCommutable>,
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EVEX_CD8<32, CD8VF>;
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}
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defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, 1>;
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defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, 1>;
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defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, 1>;
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defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp>;
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defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and, SSE_BIT_ITINS_P, 1>;
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defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or, SSE_BIT_ITINS_P, 1>;
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defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor, SSE_BIT_ITINS_P, 1>;
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defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp, SSE_BIT_ITINS_P>;
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//===----------------------------------------------------------------------===//
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// AVX-512 FP arithmetic
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@ -5081,7 +5081,7 @@ define <16 x i32> @vpandd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnon
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; GENERIC-LABEL: vpandd:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpandd:
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@ -5101,7 +5101,7 @@ define <16 x i32> @vpandnd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readno
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; GENERIC-LABEL: vpandnd:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0
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; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpandnd:
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@ -5123,7 +5123,7 @@ define <16 x i32> @vpord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone
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; GENERIC-LABEL: vpord:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpord:
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@ -5143,7 +5143,7 @@ define <16 x i32> @vpxord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnon
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; GENERIC-LABEL: vpxord:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpxord:
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@ -5163,7 +5163,7 @@ define <8 x i64> @vpandq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone s
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; GENERIC-LABEL: vpandq:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vpandq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpandq:
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@ -5182,7 +5182,7 @@ define <8 x i64> @vpandnq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone
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; GENERIC-LABEL: vpandnq:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0
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; GENERIC-NEXT: vpandnq %zmm0, %zmm1, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpandnq:
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@ -5202,7 +5202,7 @@ define <8 x i64> @vporq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ss
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; GENERIC-LABEL: vporq:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vporq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vporq:
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@ -5221,7 +5221,7 @@ define <8 x i64> @vpxorq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone s
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; GENERIC-LABEL: vpxorq:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0 # sched: [7:1.00]
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; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0
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; GENERIC-NEXT: vpxorq %zmm1, %zmm0, %zmm0 # sched: [1:1.00]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vpxorq:
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