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AMDGPU: Cleanup CreateLiveInRegister
llvm-svn: 305748
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@ -3527,18 +3527,25 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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//===----------------------------------------------------------------------===//
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SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT,
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const SDLoc &SL,
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bool RawReg) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned VirtualRegister;
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unsigned VReg;
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if (!MRI.isLiveIn(Reg)) {
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VirtualRegister = MRI.createVirtualRegister(RC);
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MRI.addLiveIn(Reg, VirtualRegister);
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VReg = MRI.createVirtualRegister(RC);
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MRI.addLiveIn(Reg, VReg);
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} else {
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VirtualRegister = MRI.getLiveInVirtReg(Reg);
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VReg = MRI.getLiveInVirtReg(Reg);
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}
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return DAG.getRegister(VirtualRegister, VT);
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if (RawReg)
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return DAG.getRegister(VReg, VT);
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return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
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}
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uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
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@ -216,10 +216,25 @@ public:
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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/// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
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/// a copy from the register.
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT,
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const SDLoc &SL,
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bool RawReg = false) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
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}
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// Returns the raw live in register rather than a copy from it.
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SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
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}
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enum ImplicitParameter {
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FIRST_IMPLICIT,
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@ -584,23 +584,23 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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return LowerImplicitParameter(DAG, VT, DL, 8);
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case Intrinsic::r600_read_tgid_x:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_X, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_X, VT);
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case Intrinsic::r600_read_tgid_y:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_Y, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_Y, VT);
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case Intrinsic::r600_read_tgid_z:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_Z, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T1_Z, VT);
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case Intrinsic::r600_read_tidig_x:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_X, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_X, VT);
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case Intrinsic::r600_read_tidig_y:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_Y, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_Y, VT);
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case Intrinsic::r600_read_tidig_z:
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return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_Z, VT);
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return CreateLiveInRegisterRaw(DAG, &AMDGPU::R600_TReg32RegClass,
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AMDGPU::T0_Z, VT);
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case Intrinsic::r600_recipsqrt_ieee:
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return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
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@ -5425,15 +5425,6 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
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return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
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}
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SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
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return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
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cast<RegisterSDNode>(VReg)->getReg(), VT);
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}
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//===----------------------------------------------------------------------===//
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// SI Inline Assembly Support
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//===----------------------------------------------------------------------===//
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@ -216,8 +216,6 @@ public:
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const override;
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SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
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MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
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