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[AArch64] Fold a floating-point divide by power of two into fp conversion.
Part of http://reviews.llvm.org/D13442 llvm-svn: 249579
This commit is contained in:
Chad Rosier
parent
b2e3d5ab9f
commit
1b95669ac4
@ -480,6 +480,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::FP_TO_SINT);
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setTargetDAGCombine(ISD::FP_TO_UINT);
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setTargetDAGCombine(ISD::FDIV);
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setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
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@ -7596,6 +7597,70 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
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return FixConv;
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}
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/// Fold a floating-point divide by power of two into fixed-point to
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/// floating-point conversion.
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static SDValue performFDivCombine(SDNode *N, SelectionDAG &DAG,
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const AArch64Subtarget *Subtarget) {
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if (!Subtarget->hasNEON())
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return SDValue();
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SDValue Op = N->getOperand(0);
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unsigned Opc = Op->getOpcode();
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if (!Op.getValueType().isVector() ||
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(Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP))
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return SDValue();
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SDValue ConstVec = N->getOperand(1);
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if (!isa<BuildVectorSDNode>(ConstVec))
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return SDValue();
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MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
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int32_t IntBits = IntTy.getSizeInBits();
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if (IntBits != 16 && IntBits != 32 && IntBits != 64)
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return SDValue();
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MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
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int32_t FloatBits = FloatTy.getSizeInBits();
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if (FloatBits != 32 && FloatBits != 64)
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return SDValue();
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// Avoid conversions where iN is larger than the float (e.g., i64 -> float).
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if (IntBits > FloatBits)
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return SDValue();
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BitVector UndefElements;
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BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
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int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, FloatBits + 1);
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if (C == -1 || C == 0 || C > FloatBits)
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return SDValue();
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MVT ResTy;
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unsigned NumLanes = Op.getValueType().getVectorNumElements();
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switch (NumLanes) {
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default:
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return SDValue();
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case 2:
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ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64;
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break;
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case 4:
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ResTy = MVT::v4i32;
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break;
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}
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SDLoc DL(N);
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SDValue ConvInput = Op.getOperand(0);
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bool IsSigned = Opc == ISD::SINT_TO_FP;
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if (IntBits < FloatBits)
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ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
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ResTy, ConvInput);
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unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfxs2fp
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: Intrinsic::aarch64_neon_vcvtfxu2fp;
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
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DAG.getConstant(IntrinsicOpcode, DL, MVT::i32), ConvInput,
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DAG.getConstant(C, DL, MVT::i32));
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}
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/// An EXTR instruction is made up of two shifts, ORed together. This helper
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/// searches for and classifies those shifts.
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static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
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@ -9470,6 +9535,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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return performFpToIntCombine(N, DAG, Subtarget);
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case ISD::FDIV:
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return performFDivCombine(N, DAG, Subtarget);
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case ISD::OR:
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return performORCombine(N, DCI, Subtarget);
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case ISD::INTRINSIC_WO_CHAIN:
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115
test/CodeGen/AArch64/fdiv_combine.ll
Normal file
115
test/CodeGen/AArch64/fdiv_combine.ll
Normal file
@ -0,0 +1,115 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-neon-syntax=apple -verify-machineinstrs -o - %s | FileCheck %s
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; Test signed conversion.
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; CHECK-LABEL: @test1
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; CHECK: scvtf.2s v0, v0, #4
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; CHECK: ret
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define <2 x float> @test1(<2 x i32> %in) {
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entry:
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%vcvt.i = sitofp <2 x i32> %in to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 16.0, float 16.0>
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ret <2 x float> %div.i
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}
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; Test unsigned conversion.
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; CHECK-LABEL: @test2
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; CHECK: ucvtf.2s v0, v0, #3
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; CHECK: ret
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define <2 x float> @test2(<2 x i32> %in) {
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entry:
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%vcvt.i = uitofp <2 x i32> %in to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 8.0, float 8.0>
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ret <2 x float> %div.i
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}
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; Test which should not fold due to non-power of 2.
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; CHECK-LABEL: @test3
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; CHECK: scvtf.2s v0, v0
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; CHECK: fmov.2s v1, #9.00000000
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; CHECK: fdiv.2s v0, v0, v1
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; CHECK: ret
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define <2 x float> @test3(<2 x i32> %in) {
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entry:
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%vcvt.i = sitofp <2 x i32> %in to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 9.0, float 9.0>
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ret <2 x float> %div.i
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}
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; Test which should not fold due to power of 2 out of range.
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; CHECK-LABEL: @test4
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; CHECK: scvtf.2s v0, v0
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; CHECK: movi.2s v1, #0x50, lsl #24
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; CHECK: fdiv.2s v0, v0, v1
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; CHECK: ret
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define <2 x float> @test4(<2 x i32> %in) {
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entry:
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%vcvt.i = sitofp <2 x i32> %in to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
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ret <2 x float> %div.i
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}
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; Test case where const is max power of 2 (i.e., 2^32).
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; CHECK-LABEL: @test5
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; CHECK: scvtf.2s v0, v0, #32
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; CHECK: ret
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define <2 x float> @test5(<2 x i32> %in) {
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entry:
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%vcvt.i = sitofp <2 x i32> %in to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
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ret <2 x float> %div.i
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}
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; Test quadword.
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; CHECK-LABEL: @test6
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; CHECK: scvtf.4s v0, v0, #2
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; CHECK: ret
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define <4 x float> @test6(<4 x i32> %in) {
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entry:
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%vcvt.i = sitofp <4 x i32> %in to <4 x float>
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%div.i = fdiv <4 x float> %vcvt.i, <float 4.0, float 4.0, float 4.0, float 4.0>
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ret <4 x float> %div.i
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}
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; Test unsigned i16 to float
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; CHECK-LABEL: @test7
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; CHECK: ushll.4s v0, v0, #0
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; CHECK: ucvtf.4s v0, v0, #1
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; CHECK: ret
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define <4 x float> @test7(<4 x i16> %in) {
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%conv = uitofp <4 x i16> %in to <4 x float>
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%shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
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ret <4 x float> %shift
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}
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; Test signed i16 to float
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; CHECK-LABEL: @test8
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; CHECK: sshll.4s v0, v0, #0
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; CHECK: scvtf.4s v0, v0, #2
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; CHECK: ret
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define <4 x float> @test8(<4 x i16> %in) {
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%conv = sitofp <4 x i16> %in to <4 x float>
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%shift = fdiv <4 x float> %conv, <float 4.0, float 4.0, float 4.0, float 4.0>
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ret <4 x float> %shift
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}
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; Can't convert i64 to float.
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; CHECK-LABEL: @test9
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; CHECK: ucvtf.2d v0, v0
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; CHECK: fcvtn v0.2s, v0.2d
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; CHECK: movi.2s v1, #0x40, lsl #24
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; CHECK: fdiv.2s v0, v0, v1
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; CHECK: ret
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define <2 x float> @test9(<2 x i64> %in) {
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%conv = uitofp <2 x i64> %in to <2 x float>
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%shift = fdiv <2 x float> %conv, <float 2.0, float 2.0>
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ret <2 x float> %shift
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}
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; CHECK-LABEL: @test10
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; CHECK: ucvtf.2d v0, v0, #1
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; CHECK: ret
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define <2 x double> @test10(<2 x i64> %in) {
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%conv = uitofp <2 x i64> %in to <2 x double>
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%shift = fdiv <2 x double> %conv, <double 2.0, double 2.0>
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ret <2 x double> %shift
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}
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