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[Hexagon] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
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@ -39,6 +39,8 @@ public:
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool enableMultipleCopyHints() const override { return true; }
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
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@ -99,8 +99,8 @@ b2:
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}
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; CHECK-LABEL: test_22:
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; CHECK: v3 = v2
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; CHECK: vcombine(v3,v2)
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; CHECK: v1 = v0
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; Result: v1:0 = vcombine(v2,v2)
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define <128 x i8> @test_22(<128 x i8> %a0, <128 x i8> %a1) #0 {
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b2:
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@ -145,8 +145,8 @@ b2:
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}
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; CHECK-LABEL: test_33:
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; CHECK: v2 = v3
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; CHECK: vcombine(v3,v2)
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; CHECK: v0 = v1
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; Result: v1:0 = vcombine(v3,v3)
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define <128 x i8> @test_33(<128 x i8> %a0, <128 x i8> %a1) #0 {
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b2:
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@ -75,9 +75,9 @@ b3:
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}
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; CHECK-LABEL: mul_nac_2
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; CHECK: r0 = memw(r0+#0)
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; CHECK: r5:4 -= mpy(r2,r0)
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; CHECK: r1:0 = combine(r5,r4)
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; CHECK: r6 = memw(r0+#0)
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; CHECK: r1:0 -= mpy(r2,r6)
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; CHECK: jumpr r31
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define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 {
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b3:
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@ -1,7 +1,7 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we are able to predicate instructions with absolute
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; addressing mode.
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; CHECK: if ({{!?}}p{{[0-3]}}) memw(##gvar) = r{{[0-9]+}}
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; CHECK: if ({{!?}}p{{[0-3]}}.new) memw(##gvar) = r{{[0-9]+}}
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@gvar = external global i32
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define i32 @test2(i32 %a, i32 %b) nounwind {
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