RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Add instruction patterns and encodings for the x86 bt instructions.

Browse Source 
llvm-svn: 61400
This commit is contained in:
Dan Gohman 2008-12-23 22:45:23 +00:00
parent 4aaf7c6b6a
commit 1ba93ac6be
4 changed files with 42 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6513,6 +6513,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::CALL: return "X86ISD::CALL";
case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
case X86ISD::BT: return "X86ISD::BT";
case X86ISD::CMP: return "X86ISD::CMP";
case X86ISD::COMI: return "X86ISD::COMI";
case X86ISD::UCOMI: return "X86ISD::UCOMI";

3
lib/Target/X86/X86ISelLowering.h
View File

@ -115,6 +115,9 @@ namespace llvm {
/// X86 compare and logical compare instructions.
CMP, COMI, UCOMI,
/// X86 bit-test instructions.
BT,
/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
/// operand produced by a CMP instruction.
SETCC,

14
lib/Target/X86/X86Instr64bit.td
View File

@ -917,6 +917,20 @@ def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
(implicit EFLAGS)]>;
} // Defs = [EFLAGS]
// Bit tests.
// TODO: BT with immediate operands.
// TODO: BTC, BTR, and BTS
let Defs = [EFLAGS] in {
def BT64rr : RI<0xA3, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
[(X86bt GR64:$src1, GR64:$src2),
(implicit EFLAGS)]>;
def BT64mr : RI<0xA3, MRMSrcMem, (outs), (ins i64mem:$src1, GR64:$src2),
"bt{q}\t{$src2, $src1|$src1, $src2}",
[(X86bt addr:$src1, GR64:$src2),
(implicit EFLAGS)]>;
} // Defs = [EFLAGS]
// Conditional moves
let Uses = [EFLAGS], isTwoAddress = 1 in {
let isCommutable = 1 in {

24
lib/Target/X86/X86InstrInfo.td
View File

@ -76,6 +76,8 @@ def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
[SDNPHasChain]>;
@ -2649,6 +2651,28 @@ def CMP32ri8 : Ii8<0x83, MRM7r,
(implicit EFLAGS)]>;
} // Defs = [EFLAGS]
// Bit tests.
// TODO: BT with immediate operands
// TODO: BTC, BTR, and BTS
let Defs = [EFLAGS] in {
def BT16rr : I<0xA3, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
[(X86bt GR16:$src1, GR16:$src2),
(implicit EFLAGS)]>, OpSize;
def BT32rr : I<0xA3, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
[(X86bt GR32:$src1, GR32:$src2),
(implicit EFLAGS)]>;
def BT16mr : I<0xA3, MRMSrcMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
[(X86bt addr:$src1, GR16:$src2),
(implicit EFLAGS)]>, OpSize;
def BT32mr : I<0xA3, MRMSrcMem, (outs), (ins i32mem:$src1, GR32:$src2),
"bt{l}\t{$src2, $src1|$src1, $src2}",
[(X86bt addr:$src1, GR32:$src2),
(implicit EFLAGS)]>;
} // Defs = [EFLAGS]
// Sign/Zero extenders
// Use movsbl intead of movsbw; we don't care about the high 16 bits
// of the register here. This has a smaller encoding and avoids a