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Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"
This reverts commit ea011ec5ed53599305de62ca5fcfd31f4b3448c3. This still causes some miscompiles, I'll follow up in the phabricator review with a sample of that issue (which is part of the sample of the previous issue).
This commit is contained in:
Martin Storsjö
parent
dc6a85256b
commit
1bc7c6b964
@ -1515,33 +1515,6 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
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return None;
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}
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// Returns a boolean that represents whether there exists a register
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// from FirstMI to the beginning of the block that can be renamed. If
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// one exists, we update Flags with its value.
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static bool updateFlagsWithRenameReg(
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Optional<bool> MaybeCanRename, LdStPairFlags &Flags, MachineInstr &FirstMI,
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MachineInstr &MI, LiveRegUnits &DefinedInBB, LiveRegUnits &UsedInBetween,
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SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
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const TargetRegisterInfo *TRI) {
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if (!DebugCounter::shouldExecute(RegRenamingCounter))
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return false;
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if (!MaybeCanRename)
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MaybeCanRename = {
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canRenameUpToDef(FirstMI, UsedInBetween, RequiredClasses, TRI)};
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if (*MaybeCanRename) {
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Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
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FirstMI, MI, DefinedInBB, UsedInBetween, RequiredClasses, TRI);
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if (MaybeRenameReg) {
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Flags.setRenameReg(*MaybeRenameReg);
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Flags.setMergeForward(true);
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return true;
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}
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}
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return false;
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}
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/// Scan the instructions looking for a load/store that can be combined with the
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/// current instruction into a wider equivalent or a load/store pair.
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MachineBasicBlock::iterator
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@ -1693,19 +1666,6 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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continue;
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}
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}
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if (TRI->isSuperOrSubRegisterEq(Reg, getLdStRegOp(MI).getReg()) &&
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ModifiedRegUnits.available(BaseReg) &&
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UsedRegUnits.available(BaseReg)) {
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bool FlagsHaveRenameReg = updateFlagsWithRenameReg(
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MaybeCanRename, Flags, FirstMI, MI, DefinedInBB, UsedInBetween,
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RequiredClasses, TRI);
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if (FlagsHaveRenameReg) {
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MBBIWithRenameReg = MBBI;
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continue;
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}
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}
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// If the destination register of one load is the same register or a
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// sub/super register of the other load, bail and keep looking. A
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// load-pair instruction with both destination registers the same is
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@ -1755,11 +1715,21 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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return MBBI;
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}
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bool FlagsHaveRenameReg = updateFlagsWithRenameReg(
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MaybeCanRename, Flags, FirstMI, MI, DefinedInBB, UsedInBetween,
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RequiredClasses, TRI);
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if (FlagsHaveRenameReg) {
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MBBIWithRenameReg = MBBI;
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if (DebugCounter::shouldExecute(RegRenamingCounter)) {
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if (!MaybeCanRename)
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MaybeCanRename = {canRenameUpToDef(FirstMI, UsedInBetween,
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RequiredClasses, TRI)};
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if (*MaybeCanRename) {
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Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
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FirstMI, MI, DefinedInBB, UsedInBetween, RequiredClasses,
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TRI);
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if (MaybeRenameReg) {
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Flags.setRenameReg(*MaybeRenameReg);
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Flags.setMergeForward(true);
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MBBIWithRenameReg = MBBI;
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}
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}
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}
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}
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// Unable to combine these instructions due to interference in between.
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@ -33,30 +33,38 @@ define void @call_byval_a64i32([64 x i32]* %incoming) {
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; CHECK-NEXT: .cfi_offset w28, -16
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; CHECK-NEXT: .cfi_offset w30, -24
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; CHECK-NEXT: .cfi_offset w29, -32
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: ldr q0, [x0, #16]
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; CHECK-NEXT: stp q1, q0, [sp]
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; CHECK-NEXT: ldr q1, [x0, #32]
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; CHECK-NEXT: str q0, [sp, #16]
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; CHECK-NEXT: ldr q0, [x0, #32]
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; CHECK-NEXT: str q0, [sp, #32]
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; CHECK-NEXT: ldr q0, [x0, #48]
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; CHECK-NEXT: stp q1, q0, [sp, #32]
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; CHECK-NEXT: ldr q1, [x0, #64]
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; CHECK-NEXT: str q0, [sp, #48]
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; CHECK-NEXT: ldr q0, [x0, #64]
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; CHECK-NEXT: str q0, [sp, #64]
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; CHECK-NEXT: ldr q0, [x0, #80]
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; CHECK-NEXT: stp q1, q0, [sp, #64]
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; CHECK-NEXT: ldr q1, [x0, #96]
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; CHECK-NEXT: str q0, [sp, #80]
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; CHECK-NEXT: ldr q0, [x0, #96]
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; CHECK-NEXT: str q0, [sp, #96]
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; CHECK-NEXT: ldr q0, [x0, #112]
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; CHECK-NEXT: stp q1, q0, [sp, #96]
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; CHECK-NEXT: ldr q1, [x0, #128]
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; CHECK-NEXT: str q0, [sp, #112]
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; CHECK-NEXT: ldr q0, [x0, #128]
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; CHECK-NEXT: str q0, [sp, #128]
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; CHECK-NEXT: ldr q0, [x0, #144]
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; CHECK-NEXT: stp q1, q0, [sp, #128]
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; CHECK-NEXT: ldr q1, [x0, #160]
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; CHECK-NEXT: str q0, [sp, #144]
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; CHECK-NEXT: ldr q0, [x0, #160]
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; CHECK-NEXT: str q0, [sp, #160]
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; CHECK-NEXT: ldr q0, [x0, #176]
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; CHECK-NEXT: stp q1, q0, [sp, #160]
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; CHECK-NEXT: ldr q1, [x0, #192]
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; CHECK-NEXT: str q0, [sp, #176]
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; CHECK-NEXT: ldr q0, [x0, #192]
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; CHECK-NEXT: str q0, [sp, #192]
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; CHECK-NEXT: ldr q0, [x0, #208]
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; CHECK-NEXT: stp q1, q0, [sp, #192]
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; CHECK-NEXT: ldr q1, [x0, #224]
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; CHECK-NEXT: str q0, [sp, #208]
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; CHECK-NEXT: ldr q0, [x0, #224]
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; CHECK-NEXT: str q0, [sp, #224]
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; CHECK-NEXT: ldr q0, [x0, #240]
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; CHECK-NEXT: stp q1, q0, [sp, #224]
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; CHECK-NEXT: str q0, [sp, #240]
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; CHECK-NEXT: bl byval_a64i32
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; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload
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; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
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@ -1,11 +1,9 @@
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; RUN: llc -mtriple=aarch64-none-unknown-linuxeabi -consthoist-gep %s -o - | FileCheck %s
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; CHECK-NOT: adrp x10, global+332
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; CHECK-NOT: add x10, x10, :lo12:global+332
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; CHECK: adrp x10, global+528
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; CHECK-NEXT: and w12, w8, #0xffffff
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; CHECK-NEXT: ldr w8, [x11]
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; CHECK-NEXT: add x10, x10, :lo12:global+528
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; CHECK-NOT: adrp x10, global+332
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; CHECK-NOT: add x10, x10, :lo12:global+332
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; CHECK: adrp x10, global+528
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; CHECK-NEXT: add x10, x10, :lo12:global+528
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%struct.blam = type { %struct.bar, %struct.bar.0, %struct.wobble, %struct.wombat, i8, i16, %struct.snork.2, %struct.foo, %struct.snork.3, %struct.wobble.4, %struct.quux, [9 x i16], %struct.spam, %struct.zot }
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%struct.bar = type { i8, i8, %struct.snork }
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@ -1117,7 +1117,7 @@ define void @store-pair-post-indexed-double() nounwind {
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define void @post-indexed-sub-word(i32* %a, i32* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-word
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; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}], #-8
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; CHECK: stp w{{[0-9]+}}, w{{[0-9]+}}, [x0, #-4]
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; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}], #-8
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br label %for.body
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for.body:
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%phi1 = phi i32* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1141,7 +1141,7 @@ end:
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define void @post-indexed-sub-doubleword(i64* %a, i64* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-doubleword
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; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #-16
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; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0, #-8]
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; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #-16
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br label %for.body
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for.body:
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%phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1165,7 +1165,7 @@ end:
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define void @post-indexed-sub-quadword(<2 x i64>* %a, <2 x i64>* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-quadword
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; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}], #-32
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; CHECK: stp q{{[0-9]+}}, q{{[0-9]+}}, [x0, #-16]
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; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}], #-32
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br label %for.body
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for.body:
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%phi1 = phi <2 x i64>* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1189,7 +1189,7 @@ end:
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define void @post-indexed-sub-float(float* %a, float* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-float
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; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}], #-8
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; CHECK: stp s{{[0-9]+}}, s{{[0-9]+}}, [x0, #-4]
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; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}], #-8
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br label %for.body
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for.body:
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%phi1 = phi float* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1213,7 +1213,7 @@ end:
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define void @post-indexed-sub-double(double* %a, double* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-double
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; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}], #-16
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; CHECK: stp d{{[0-9]+}}, d{{[0-9]+}}, [x0, #-8]
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; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}], #-16
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br label %for.body
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for.body:
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%phi1 = phi double* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1237,7 +1237,7 @@ end:
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define void @post-indexed-sub-doubleword-offset-min(i64* %a, i64* %b, i64 %count) nounwind {
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; CHECK-LABEL: post-indexed-sub-doubleword-offset-min
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; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #-256
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; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0], #-256
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; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #-256
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br label %for.body
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for.body:
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%phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ]
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@ -1262,7 +1262,8 @@ define void @post-indexed-doubleword-offset-out-of-range(i64* %a, i64* %b, i64 %
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; CHECK-LABEL: post-indexed-doubleword-offset-out-of-range
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; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}]
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; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256
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; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0], #256
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; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}]
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; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256
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br label %for.body
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for.body:
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@ -544,161 +544,3 @@ body: |
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RET undef $lr
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...
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# During ISel, the order of load/store pairs can be optimized and changed
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# so that only a single register is used. Due to this register reuse, LDP/STPs
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# are not generated. These tests check that an STP instruction will be
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# generated after register renaming is attempted.
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...
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---
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#
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# CHECK-LABEL: name: ldst32
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# CHECK: liveins: $x0, $x1
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# CHECK: $q1 = LDRQui renamable $x1, 1 :: (load 16)
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# CHECK-NEXT: renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
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# CHECK-NEXT: STPQi killed renamable $q0, killed $q1, killed renamable $x0, 0 :: (store 16, align 32)
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# CHECK-NEXT: RET undef $lr
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#
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name: ldst32
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0', virtual-reg: '' }
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- { reg: '$x1', virtual-reg: '' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: false
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
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STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, basealign 32)
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renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
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STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 32)
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RET undef $lr
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...
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---
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#
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# CHECK-LABEL: name: ldst64
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# CHECK: liveins: $x0, $x1
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# CHECK: $q1 = LDRQui renamable $x1, 1 :: (load 16)
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# CHECK-NEXT: renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 64)
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# CHECK-NEXT: STPQi killed renamable $q0, killed $q1, killed renamable $x0, 0 :: (store 16, align 64)
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# CHECK-NEXT: RET undef $lr
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#
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name: ldst64
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0', virtual-reg: '' }
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- { reg: '$x1', virtual-reg: '' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: false
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
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STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, basealign 64)
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renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 64)
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STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 64)
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RET undef $lr
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...
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---
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#
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# CHECK-LABEL: name: ldst128
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# CHECK: liveins: $x0, $x1
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# CHECK: $q1 = LDRQui renamable $x1, 1 :: (load 16)
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# CHECK-NEXT: renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 128)
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# CHECK-NEXT: STPQi killed renamable $q0, killed $q1, killed renamable $x0, 0 :: (store 16, align 128)
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# CHECK-NEXT: RET undef $lr
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#
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name: ldst128
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0', virtual-reg: '' }
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- { reg: '$x1', virtual-reg: '' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: false
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
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STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, basealign 128)
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renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 128)
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STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 128)
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RET undef $lr
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...
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---
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#
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# CHECK-LABEL: name: ldst-no-reg-available
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# CHECK: liveins: $x0, $x1, $q1, $q2, $q3, $q4, $q5, $q6, $q7, $q8, $q9, $q10
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# CHECK: renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
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# CHECK-NEXT: STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, align 32)
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# CHECK-NEXT: renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
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# CHECK-NEXT: STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 32)
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# CHECK-NEXT: RET undef $lr
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#
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name: ldst-no-reg-available
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo:
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hasRedZone: false
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $q1, $q2, $q3, $q4, $q5, $q6, $q7, $q8, $q9, $q10
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renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
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STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, basealign 32)
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renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
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STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 32)
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RET undef $lr
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...
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---
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#
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# CHECK-LABEL: name: ldst-basereg-modified
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# CHECK: liveins: $x0, $x1
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||||
# CHECK: renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
|
||||
# CHECK-NEXT: STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, align 32)
|
||||
# CHECK-NEXT: renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
|
||||
# CHECK-NEXT: STRHHui $wzr, renamable $x0, 12 :: (store 2, align 8)
|
||||
# CHECK-NEXT: STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 32)
|
||||
# CHECK-NEXT: RET undef $lr
|
||||
#
|
||||
name: ldst-basereg-modified
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$x0' }
|
||||
- { reg: '$x1' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
maxCallFrameSize: 0
|
||||
machineFunctionInfo:
|
||||
hasRedZone: false
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x0, $x1
|
||||
renamable $q0 = LDRQui renamable $x1, 1 :: (load 16)
|
||||
STRQui killed renamable $q0, renamable $x0, 1 :: (store 16, basealign 32)
|
||||
renamable $q0 = LDRQui killed renamable $x1, 0 :: (load 16, align 32)
|
||||
STRHHui $wzr, renamable $x0, 12 :: (store 2, align 8)
|
||||
STRQui killed renamable $q0, killed renamable $x0, 0 :: (store 16, align 32)
|
||||
RET undef $lr
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user