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https://github.com/RPCS3/llvm-mirror.git
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[AArch64][GlobalISel] Legalize G_FEXP2
Same as G_EXP. Add a test, and update legalizer-info-validation.mir and f16-instructions.ll. Differential Revision: https://reviews.llvm.org/D60165 llvm-svn: 357605
This commit is contained in:
Jessica Paquette
parent
4203e42e17
commit
1bef4155b3
@ -244,6 +244,9 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
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case TargetOpcode::G_FEXP:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
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case TargetOpcode::G_FEXP2:
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assert((Size == 32 || Size == 64) && "Unsupported size");
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return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
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case TargetOpcode::G_FREM:
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return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
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case TargetOpcode::G_FPOW:
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@ -368,7 +371,8 @@ LegalizerHelper::libcall(MachineInstr &MI) {
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case TargetOpcode::G_FLOG10:
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case TargetOpcode::G_FLOG:
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case TargetOpcode::G_FLOG2:
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case TargetOpcode::G_FEXP: {
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FEXP2: {
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if (Size > 64) {
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LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
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return UnableToLegalize;
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@ -1345,6 +1349,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_FLOG2:
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case TargetOpcode::G_FSQRT:
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FEXP2:
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assert(TypeIdx == 0);
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Observer.changingInstr(MI);
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@ -146,7 +146,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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.legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16});
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getActionDefinitionsBuilder(
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{G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2, G_FEXP})
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{G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2, G_FEXP, G_FEXP2})
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// We need a call for these, so we always need to scalarize.
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.scalarize(0)
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// Regardless of FP16 support, widen 16-bit elements to 32-bits.
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252
test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
Normal file
252
test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
Normal file
@ -0,0 +1,252 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: test_v4f16.exp2
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.exp2
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
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; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
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; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT1]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
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; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT2]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
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; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT3]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
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; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_FEXP2 %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.exp2
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.exp2
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
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; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
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; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT1]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
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; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT2]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
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; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT3]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
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; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT4]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
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; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT5]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32)
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; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT6]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32)
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; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[FPEXT7]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
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; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_FEXP2 %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.exp2
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.exp2
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV1]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
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; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_FEXP2 %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.exp2
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.exp2
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV1]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV2]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[UV3]](s32)
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; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
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; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_FEXP2 %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.exp2
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.exp2
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $d0 = COPY [[UV]](s64)
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; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
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; CHECK: $d0 = COPY [[UV1]](s64)
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; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY1]](s64), [[COPY2]](s64)
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; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s64>) = COPY $q0
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%1:_(<2 x s64>) = G_FEXP2 %0
|
||||
$q0 = COPY %1(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_exp2_half
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $h0
|
||||
; CHECK-LABEL: name: test_exp2_half
|
||||
; CHECK: liveins: $h0
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
|
||||
; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
|
||||
; CHECK: $s0 = COPY [[FPEXT]](s32)
|
||||
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
|
||||
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
|
||||
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
|
||||
; CHECK: $h0 = COPY [[FPTRUNC]](s16)
|
||||
; CHECK: RET_ReallyLR implicit $h0
|
||||
%0:_(s16) = COPY $h0
|
||||
%1:_(s16) = G_FEXP2 %0
|
||||
$h0 = COPY %1(s16)
|
||||
RET_ReallyLR implicit $h0
|
||||
@ -259,7 +259,7 @@
|
||||
# DEBUG: .. the first uncovered type index: 1, OK
|
||||
#
|
||||
# DEBUG-NEXT: G_FEXP2 (opcode {{[0-9]+}}): 1 type index
|
||||
# DEBUG: .. type index coverage check SKIPPED: no rules defined
|
||||
# DEBUG: .. the first uncovered type index: 1, OK
|
||||
#
|
||||
# DEBUG-NEXT: G_FLOG (opcode {{[0-9]+}}): 1 type index
|
||||
# DEBUG: .. the first uncovered type index: 1, OK
|
||||
|
||||
@ -919,6 +919,15 @@ define half @test_exp(half %a) #0 {
|
||||
; CHECK-COMMON-NEXT: fcvt h0, s0
|
||||
; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-COMMON-NEXT: ret
|
||||
|
||||
; GISEL-LABEL: test_exp2:
|
||||
; GISEL-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; GISEL-NEXT: mov x29, sp
|
||||
; GISEL-NEXT: fcvt s0, h0
|
||||
; GISEL-NEXT: bl {{_?}}exp2f
|
||||
; GISEL-NEXT: fcvt h0, s0
|
||||
; GISEL-NEXT: ldp x29, x30, [sp], #16
|
||||
; GISEL-NEXT: ret
|
||||
define half @test_exp2(half %a) #0 {
|
||||
%r = call half @llvm.exp2.f16(half %a)
|
||||
ret half %r
|
||||
|
||||
Loading…
Reference in New Issue
Block a user