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[RISCV] Update alu8.ll and alu16.ll test cases

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The srli test in alu8.ll was a no-op, as it shifted by 8 bits. Fix this, and 
also change the immediate in alu16.ll as shifted by something other than a 
poewr of 8 is more interesting.

llvm-svn: 343958
This commit is contained in:
Alex Bradbury 2018-10-08 09:08:51 +00:00
parent 81c89f9e0f
commit 1c67f6027a
2 changed files with 9 additions and 5 deletions
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6
test/CodeGen/RISCV/alu16.ll
View File

@ -82,11 +82,11 @@ define i16 @srli(i16 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: addi a1, a1, -64
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: srli a0, a0, 6
; RV32I-NEXT: ret
%1 = lshr i16 %a, 8
%1 = lshr i16 %a, 6
ret i16 %1
}

8
test/CodeGen/RISCV/alu8.ll
View File

@ -79,16 +79,20 @@ define i8 @slli(i8 %a) nounwind {
define i8 @srli(i8 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 192
; RV32I-NEXT: srli a0, a0, 6
; RV32I-NEXT: ret
%1 = lshr i8 %a, 8
%1 = lshr i8 %a, 6
ret i8 %1
}
define i8 @srai(i8 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 29
; RV32I-NEXT: ret
%1 = ashr i8 %a, 9
%1 = ashr i8 %a, 5
ret i8 %1
}