From 1c6e85f4566347be9647934d30117ac630ee707d Mon Sep 17 00:00:00 2001 From: Jeroen Ketema Date: Mon, 21 Sep 2015 20:28:04 +0000 Subject: [PATCH] [ARM] Do not scale vext with a factor The vext pseudo-instruction takes the number of elements that need to be extracted, not the number of bytes. Hence, use the number of elements directly instead of scaling them with a factor. Reviewers: Silviu Baranga, James Molloy (not reflected in the differential revision) Differential Revision: http://reviews.llvm.org/D12974 llvm-svn: 248208 --- lib/Target/ARM/ARMISelLowering.cpp | 10 +--------- test/CodeGen/ARM/vzip.ll | 11 +++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 3c66d56b6a3..6dcb778061f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5515,13 +5515,6 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, return SDValue(); } -/// getExtFactor - Determine the adjustment factor for the position when -/// generating an "extract from vector registers" instruction. -static unsigned getExtFactor(SDValue &V) { - EVT EltType = V.getValueType().getVectorElementType(); - return EltType.getSizeInBits() / 8; -} - // Gather data to see if the operation can be modelled as a // shuffle in combination with VEXTs. SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, @@ -5652,11 +5645,10 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, DAG.getConstant(NumSrcElts, dl, MVT::i32)); - unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1); Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, VEXTSrc2, - DAG.getConstant(Imm, dl, MVT::i32)); + DAG.getConstant(Src.MinElt, dl, MVT::i32)); Src.WindowBase = -Src.MinElt; } } diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index 24386a236f4..29385d0cc9d 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -305,3 +305,14 @@ entry: store <4 x i32> %0, <4 x i32>* %B ret void } + +define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) { +entry: + ; CHECK-LABEL: vzip_vext_factor + ; CHECK: vext.16 d16, d16, d17, #3 + ; CHECK: vzip + %tmp1 = load <8 x i16>, <8 x i16>* %A + %0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> + store <4 x i16> %0, <4 x i16>* %B + ret void +}