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[ARM] Do not scale vext with a factor

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The vext pseudo-instruction takes the number of elements that need to be
extracted, not the number of bytes. Hence, use the number of elements
directly instead of scaling them with a factor.

Reviewers: Silviu Baranga, James Molloy
(not reflected in the differential revision)

Differential Revision: http://reviews.llvm.org/D12974

llvm-svn: 248208
This commit is contained in:
Jeroen Ketema 2015-09-21 20:28:04 +00:00
parent 4173405f38
commit 1c6e85f456
2 changed files with 12 additions and 9 deletions
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10
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -5515,13 +5515,6 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
return SDValue(); return SDValue();
} }
/// getExtFactor - Determine the adjustment factor for the position when
/// generating an "extract from vector registers" instruction.
static unsigned getExtFactor(SDValue &V) {
EVT EltType = V.getValueType().getVectorElementType();
return EltType.getSizeInBits() / 8;
}
// Gather data to see if the operation can be modelled as a // Gather data to see if the operation can be modelled as a
// shuffle in combination with VEXTs. // shuffle in combination with VEXTs.
SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
@ -5652,11 +5645,10 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
SDValue VEXTSrc2 = SDValue VEXTSrc2 =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
DAG.getConstant(NumSrcElts, dl, MVT::i32)); DAG.getConstant(NumSrcElts, dl, MVT::i32));
unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
VEXTSrc2, VEXTSrc2,
DAG.getConstant(Imm, dl, MVT::i32)); DAG.getConstant(Src.MinElt, dl, MVT::i32));
Src.WindowBase = -Src.MinElt; Src.WindowBase = -Src.MinElt;
} }
} }

11
test/CodeGen/ARM/vzip.ll
View File

@ -305,3 +305,14 @@ entry:
store <4 x i32> %0, <4 x i32>* %B store <4 x i32> %0, <4 x i32>* %B
ret void ret void
} }
define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) {
entry:
; CHECK-LABEL: vzip_vext_factor
; CHECK: vext.16 d16, d16, d17, #3
; CHECK: vzip
%tmp1 = load <8 x i16>, <8 x i16>* %A
%0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 4, i32 5, i32 3>
store <4 x i16> %0, <4 x i16>* %B
ret void
}