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Fix up a few more spots of addrmode2 (or not) changes that were

missed. Update some comments accordingly.

Fixes rdar://8652289

llvm-svn: 118888
This commit is contained in:
Eric Christopher 2010-11-12 09:48:30 +00:00
parent f867bfd906
commit 1ca7518097

View File

@ -460,7 +460,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
TII.get(ARM::t2LDRpci), DestReg)
.addConstantPoolIndex(Idx));
else
// The extra reg and immediate are for addrmode2.
// The extra immediate is for addrmode2.
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDRcp), DestReg)
.addConstantPoolIndex(Idx)
@ -505,11 +505,11 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
if (RelocM == Reloc::PIC_)
MIB.addImm(Id);
} else {
// The extra reg and immediate are for addrmode2.
// The extra immediate is for addrmode2.
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
DestReg)
.addConstantPoolIndex(Idx)
.addReg(0).addImm(0);
.addImm(0);
}
AddOptionalDefs(MIB);
return DestReg;
@ -790,9 +790,15 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
if (isFloat)
Offset /= 4;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Base).addImm(Offset));
// LDRH needs an additional operand.
if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Base).addReg(0).addImm(Offset));
else
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Base).addImm(Offset));
return true;
}