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[Power9]Legalize and emit code for converting Unsigned HWord/Char to Quad-Precision
Legalize and emit code for converting unsigned HWord/Char to QP: xscvsdqp xscvudqp Only covering patterns for unsigned forms cause we don't have part-word sign-extending integer loads into VSX registers. Differential Revision: https://reviews.llvm.org/D45494 llvm-svn: 330278
This commit is contained in:
Lei Huang
parent
4ec41556e3
commit
1cdba03f1f
@ -3142,6 +3142,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))),
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(f128 (XSCVUDQP (LXSD ixaddr:$src)))>;
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// Convert Unsigned HWord in memory -> QP
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def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)),
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(f128 (XSCVUDQP (LXSIHZX xaddr:$src)))>;
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// Convert Unsigned Byte in memory -> QP
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def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)),
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(f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>;
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} // end HasP9Vector, AddedComplexity
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let Predicates = [HasP9Vector] in {
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@ -6,6 +6,8 @@
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@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
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@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
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@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
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@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
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@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
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; Function Attrs: norecurse nounwind
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define void @sdwConv2qp(fp128* nocapture %a, i64 %b) {
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@ -297,3 +299,142 @@ entry:
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uhwConv2qp(fp128* nocapture %a, i16 zeroext %b) {
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entry:
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%conv = uitofp i16 %b to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uhwConv2qp
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; CHECK: mtvsrwz [[REG:[0-9]+]], 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uhwConv2qp_02(fp128* nocapture %a, i16* nocapture readonly %b) {
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entry:
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%0 = load i16, i16* %b, align 2
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%conv = uitofp i16 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uhwConv2qp_02
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; CHECK: lxsihzx [[REG:[0-9]+]], 0, 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uhwConv2qp_03(fp128* nocapture %a) {
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entry:
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%0 = load i16, i16* getelementptr inbounds
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([5 x i16], [5 x i16]* @uhwMem, i64 0, i64 3), align 2
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%conv = uitofp i16 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uhwConv2qp_03
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; CHECK: addis [[REG0:[0-9]+]], 2, .LC4@toc@ha
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; CHECK: ld [[REG0]], .LC4@toc@l([[REG0]])
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; CHECK: addi [[REG0]], [[REG0]], 6
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; CHECK: lxsihzx [[REG:[0-9]+]], 0, [[REG0]]
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uhwConv2qp_04(fp128* nocapture %a, i16 zeroext %b,
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i16* nocapture readonly %c) {
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entry:
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%conv = zext i16 %b to i32
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%0 = load i16, i16* %c, align 2
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%conv1 = zext i16 %0 to i32
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%add = add nuw nsw i32 %conv1, %conv
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%conv2 = sitofp i32 %add to fp128
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store fp128 %conv2, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uhwConv2qp_04
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; CHECK: lhz [[REG0:[0-9]+]], 0(5)
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; CHECK: add 4, [[REG0]], 4
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; CHECK: mtvsrwa [[REG:[0-9]+]], 4
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @ubConv2qp(fp128* nocapture %a, i8 zeroext %b) {
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entry:
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%conv = uitofp i8 %b to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: ubConv2qp
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; CHECK: mtvsrwz [[REG:[0-9]+]], 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @ubConv2qp_02(fp128* nocapture %a, i8* nocapture readonly %b) {
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entry:
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%0 = load i8, i8* %b, align 1
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%conv = uitofp i8 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: ubConv2qp_02
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; CHECK: lxsibzx [[REG:[0-9]+]], 0, 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @ubConv2qp_03(fp128* nocapture %a) {
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entry:
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%0 = load i8, i8* getelementptr inbounds
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([5 x i8], [5 x i8]* @ubMem, i64 0, i64 2), align 1
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%conv = uitofp i8 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: ubConv2qp_03
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; CHECK: addis [[REG0:[0-9]+]], 2, .LC5@toc@ha
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; CHECK: ld [[REG0]], .LC5@toc@l([[REG0]])
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; CHECK: addi [[REG0]], [[REG0]], 2
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; CHECK: lxsibzx [[REG:[0-9]+]], 0, [[REG0]]
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @ubConv2qp_04(fp128* nocapture %a, i8 zeroext %b,
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i8* nocapture readonly %c) {
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entry:
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%conv = zext i8 %b to i32
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%0 = load i8, i8* %c, align 1
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%conv1 = zext i8 %0 to i32
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%add = add nuw nsw i32 %conv1, %conv
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%conv2 = sitofp i32 %add to fp128
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store fp128 %conv2, fp128* %a, align 16
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ret void
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; CHECK-LABEL: ubConv2qp_04
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; CHECK: lbz [[REG0:[0-9]+]], 0(5)
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; CHECK: add 4, [[REG0]], 4
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; CHECK: mtvsrwa [[REG:[0-9]+]], 4
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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