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Update the cpu specified on some PPC regression tests
Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. llvm-svn: 195977
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@ -1,4 +1,4 @@
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; RUN: llc < %s | FileCheck %s
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; RUN: llc -mcpu=g5 < %s | FileCheck %s
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;; Formerly crashed, see PR 1508
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
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target triple = "powerpc64-apple-darwin8"
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@ -1,4 +1,4 @@
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; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
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; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s
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; RUN: llc -march=ppc64 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s
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; RUN: llc -march=ppc64 -mcpu=g5 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s
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; Check that the peephole optimizer knows about sext and zext instructions.
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; CHECK: test1sext
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define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
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; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=ppc64 -O0 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
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; RUN: llc -mcpu=ppc64 -O0 -fast-isel=false < %s | FileCheck %s
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; This tests receiving and re-passing parameters consisting of structures
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; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc64 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple="powerpc-unknown-linux-gnu" < %s | FileCheck %s
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; RUN: llc -mtriple="powerpc-unknown-linux-gnu" -mcpu=ppc64 < %s | FileCheck %s
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; PR15286
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%va_list = type {i8, i8, i16, i8*, i8*}
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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; RUN: llc -mcpu=ppc64 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,4 +1,4 @@
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; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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; RUN: llc -mcpu=ppc64 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -1,6 +1,6 @@
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-freebsd10.0"
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; RUN: llc -O1 < %s -march=ppc64 | FileCheck %s
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; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck %s
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@a = thread_local global i32 0, align 4
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@ -1,7 +1,7 @@
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-freebsd10.0"
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; RUN: llc -O0 < %s -march=ppc64 | FileCheck -check-prefix=OPT0 %s
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; RUN: llc -O1 < %s -march=ppc64 | FileCheck -check-prefix=OPT1 %s
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; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
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; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
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@a = thread_local global i32 0, align 4
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