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Add ppc partial-word ATOMIC_CMP_SWAP.
llvm-svn: 55554
This commit is contained in:
Dale Johannesen
parent
c1c53221c5
commit
1cfbb25e75
@ -3971,12 +3971,12 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
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// slw mask, mask2, shift
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// loopMBB:
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// l[wd]arx tmpDest, ptr
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// lwarx tmpDest, ptr
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// add tmp, tmpDest, incr2
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// andc tmp2, tmpDest, mask
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// and tmp3, tmp, mask
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// or tmp4, tmp3, tmp2
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// st[wd]cx. tmp4, ptr
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// stwcx. tmp4, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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// srw dest, tmpDest, shift
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@ -4221,8 +4221,147 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// exitMBB:
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// ...
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BB = exitMBB;
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}
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else {
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} else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
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MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
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// We must use 64-bit registers for addresses when targeting 64-bit,
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// since we're actually doing arithmetic on them. Other registers
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// can be 32-bit.
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bool is64bit = PPCSubTarget.isPPC64();
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bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptrA = MI->getOperand(1).getReg();
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unsigned ptrB = MI->getOperand(2).getReg();
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unsigned oldval = MI->getOperand(3).getReg();
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unsigned newval = MI->getOperand(4).getReg();
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MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loop1MBB);
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F->insert(It, loop2MBB);
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F->insert(It, midMBB);
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F->insert(It, exitMBB);
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exitMBB->transferSuccessors(BB);
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MachineRegisterInfo &RegInfo = F->getRegInfo();
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const TargetRegisterClass *RC =
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is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
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(const TargetRegisterClass *) &PPC::G8RCRegClass;
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unsigned PtrReg = RegInfo.createVirtualRegister(RC);
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unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
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unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
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unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
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unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
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unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
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unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
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unsigned MaskReg = RegInfo.createVirtualRegister(RC);
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unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
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unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
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unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
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unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
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unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
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unsigned Ptr1Reg;
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unsigned TmpReg = RegInfo.createVirtualRegister(RC);
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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BB->addSuccessor(loop1MBB);
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// The 4-byte load must be aligned, while a char or short may be
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// anywhere in the word. Hence all this nasty bookkeeping code.
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// add ptr1, ptrA, ptrB [copy if ptrA==0]
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// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
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// xor shift, shift1, 24 [16]
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// rlwinm ptr, ptr1, 0, 0, 29
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// slw newval2, newval, shift
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// slw oldval2, oldval,shift
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// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
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// slw mask, mask2, shift
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// and newval3, newval2, mask
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// and oldval3, oldval2, mask
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// loop1MBB:
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// lwarx tmpDest, ptr
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// and tmp, tmpDest, mask
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// cmpw tmp, oldval3
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// bne- midMBB
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// loop2MBB:
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// andc tmp2, tmpDest, mask
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// or tmp4, tmp2, newval3
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// stwcx. tmp4, ptr
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// bne- loop1MBB
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// b exitBB
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// midMBB:
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// stwcx. tmpDest, ptr
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// exitBB:
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// srw dest, tmpDest, shift
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if (ptrA!=PPC::R0) {
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Ptr1Reg = RegInfo.createVirtualRegister(RC);
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BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
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.addReg(ptrA).addReg(ptrB);
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} else {
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Ptr1Reg = ptrB;
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}
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BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
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.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
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BuildMI(BB, TII->get(is64bit ? PPC::XOR8 : PPC::XOR), ShiftReg)
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.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
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if (is64bit)
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BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
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.addReg(Ptr1Reg).addImm(0).addImm(61);
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else
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BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
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.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
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BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
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.addReg(newval).addReg(ShiftReg);
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BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
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.addReg(oldval).addReg(ShiftReg);
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if (is8bit)
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BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
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else {
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BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
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BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
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}
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BuildMI(BB, TII->get(PPC::SLW), MaskReg)
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.addReg(Mask2Reg).addReg(ShiftReg);
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BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
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.addReg(NewVal2Reg).addReg(MaskReg);
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BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
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.addReg(OldVal2Reg).addReg(MaskReg);
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BB = loop1MBB;
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BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
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.addReg(PPC::R0).addReg(PtrReg);
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BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
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BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
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.addReg(TmpReg).addReg(OldVal3Reg);
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
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BB->addSuccessor(loop2MBB);
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BB->addSuccessor(midMBB);
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BB = loop2MBB;
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BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
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BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
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BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
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.addReg(PPC::R0).addReg(PtrReg);
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
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BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
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BB->addSuccessor(loop1MBB);
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BB->addSuccessor(exitMBB);
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BB = midMBB;
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BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
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.addReg(PPC::R0).addReg(PtrReg);
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BB->addSuccessor(exitMBB);
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// exitMBB:
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// ...
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BB = exitMBB;
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BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
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} else {
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assert(0 && "Unexpected instr type to insert");
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}
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