RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

[PowerPC] Fix powerpcspe subtarget enablement in llvm backend

Browse Source 
Summary:
As currently written, -target powerpcspe will enable SPE regardless of
disabling the feature later on in the command line.  Instead, change
this to just set a default CPU to 'e500' instead of a generic CPU.

As part of this, add FeatureSPE to the e500 definition.

Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D72673
This commit is contained in:
Justin Hibbits 2020-01-13 20:06:29 -06:00
parent fb33bc86b6
commit 1d2d48be7e
2 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/PowerPC/PPC.td
View File

@ -442,7 +442,7 @@ def : ProcessorModel<"g5", G5Model,
def : ProcessorModel<"e500", PPCE500Model,
[DirectiveE500,
FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB]>;
FeatureISEL, FeatureMFTB, FeatureSPE]>;
def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE,

5
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -127,6 +127,8 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
// If cross-compiling with -march=ppc64le without -mcpu
if (TargetTriple.getArch() == Triple::ppc64le)
CPUName = "ppc64le";
else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
CPUName = "e500";
else
CPUName = "generic";
}
@ -151,9 +153,6 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
TargetTriple.isMusl())
SecurePlt = true;
if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
HasSPE = true;
if (HasSPE && IsPPC64)
report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))