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it's pointed out that R11 can be used for magic things, and doing things just for 64-bit registers is silly. Just optimize 3 more.
llvm-svn: 157699
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@ -35,7 +35,7 @@ def RetCC_X86Common : CallingConv<[
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CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
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CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
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CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
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CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R11]>>,
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CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
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// Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
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// can only be used by ABI non-compliant code. If the target doesn't have XMM
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@ -1,17 +0,0 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.3.0"
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define { i8*, i64, i64*, i64 } @copy_4(i8* %a, i64 %b, i64* %c, i64 %d) nounwind {
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entry:
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%0 = insertvalue { i8*, i64, i64*, i64 } undef, i8* %a, 0
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%1 = insertvalue { i8*, i64, i64*, i64 } %0, i64 %b, 1
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%2 = insertvalue { i8*, i64, i64*, i64 } %1, i64* %c, 2
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%3 = insertvalue { i8*, i64, i64*, i64 } %2, i64 %d, 3
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ret { i8*, i64, i64*, i64 } %3
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}
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; CHECK: copy_4:
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; CHECK-NOT: (%rdi)
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; CHECK: ret
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16
test/CodeGen/X86/pass-three.ll
Normal file
16
test/CodeGen/X86/pass-three.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.3.0"
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define { i8*, i64, i64* } @copy_3(i8* %a, i64 %b, i64* %c) nounwind {
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entry:
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%0 = insertvalue { i8*, i64, i64* } undef, i8* %a, 0
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%1 = insertvalue { i8*, i64, i64* } %0, i64 %b, 1
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%2 = insertvalue { i8*, i64, i64* } %1, i64* %c, 2
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ret { i8*, i64, i64* } %2
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}
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; CHECK: copy_3:
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; CHECK-NOT: (%rdi)
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; CHECK: ret
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