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[RISCV] Remove isel patterns for Zbs *W instructions.
These instructions have been removed from the 0.94 bitmanip spec. We should focus on optimizing the codegen without using them. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D95302
This commit is contained in:
Craig Topper
parent
dd352986b6
commit
1d3e28399b
@ -90,18 +90,6 @@ def BSETINVXForm : SDNodeXForm<imm, [{
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SDLoc(N), N->getValueType(0));
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}]>;
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// Similar to above, but makes sure the immediate has 33 sign bits. When used
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// with an AND/OR/XOR where the other operand has at least 33 sign bits, the
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// result will have 33 sign bits. This can match BCLRIW/BSETIW/BINVIW.
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def BCLRWMask : ImmLeaf<i64, [{
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// After checking the sign bits, truncate to 32 bits for power of 2 check.
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return isInt<32>(Imm) && !isInt<12>(Imm) && isPowerOf2_32(~Imm);
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}]>;
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def BSETINVWMask : ImmLeaf<i64, [{
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return isInt<32>(Imm) && !isInt<12>(Imm) && isPowerOf2_32(Imm);
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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@ -380,6 +368,8 @@ def RORW : ALUW_rr<0b0110000, 0b101, "rorw">, Sched<[]>;
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} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
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let Predicates = [HasStdExtZbs, IsRV64] in {
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// NOTE: These instructions have been removed from the 0.94 spec. As a result
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// we have no isel patterns for them.
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def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>;
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def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>;
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def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
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@ -404,6 +394,8 @@ let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
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def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[]>;
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let Predicates = [HasStdExtZbs, IsRV64] in {
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// NOTE: These instructions have been removed from the 0.94 spec. As a result
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// we have no isel patterns for them.
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def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">,
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Sched<[]>;
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def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">,
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@ -954,34 +946,6 @@ def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
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(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
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} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
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let Predicates = [HasStdExtZbs, IsRV64] in {
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def : Pat<(and (not (riscv_sllw 1, GPR:$rs2)), (assertsexti32 GPR:$rs1)),
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(BCLRW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (and (not (riscv_sllw 1, GPR:$rs2)), GPR:$rs1), i32),
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(BCLRW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(or (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)),
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(BSETW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (or (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32),
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(BSETW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(xor (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)),
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(BINVW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (xor (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32),
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(BINVW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(and (riscv_srlw GPR:$rs1, GPR:$rs2), 1),
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(BEXTW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(riscv_sllw 1, GPR:$rs2),
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(BSETW X0, GPR:$rs2)>;
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def : Pat<(and (assertsexti32 GPR:$rs1), BCLRWMask:$mask),
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(BCLRIW GPR:$rs1, (BCLRXForm imm:$mask))>;
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def : Pat<(or (assertsexti32 GPR:$rs1), BSETINVWMask:$mask),
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(BSETIW GPR:$rs1, (BSETINVXForm imm:$mask))>;
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def : Pat<(xor (assertsexti32 GPR:$rs1), BSETINVWMask:$mask),
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(BINVIW GPR:$rs1, (BSETINVXForm imm:$mask))>;
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} // Predicates = [HasStdExtZbs, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def : Pat<(sext_inreg (SLOIPat GPR:$rs1, uimm5:$shamt), i32),
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(SLOIW GPR:$rs1, uimm5:$shamt)>;
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@ -17,12 +17,17 @@ define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbclr_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bclrw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: andn a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclr_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bclrw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: not a1, a1
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; RV64IBS-NEXT: and a0, a1, a0
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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@ -42,12 +47,17 @@ define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbclr_i32_no_mask:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bclrw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: andn a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclr_i32_no_mask:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bclrw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: not a1, a1
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; RV64IBS-NEXT: and a0, a1, a0
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; RV64IBS-NEXT: ret
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%shl = shl i32 1, %b
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%neg = xor i32 %shl, -1
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@ -69,13 +79,20 @@ define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
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; RV64IB-LABEL: sbclr_i32_load:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: bclrw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: andn a0, a0, a1
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; RV64IB-NEXT: sext.w a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclr_i32_load:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: lw a0, 0(a0)
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; RV64IBS-NEXT: bclrw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: not a1, a1
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; RV64IBS-NEXT: and a0, a1, a0
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; RV64IBS-NEXT: sext.w a0, a0
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; RV64IBS-NEXT: ret
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%a = load i32, i32* %p
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%shl = shl i32 1, %b
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@ -143,12 +160,16 @@ define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbset_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bsetw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: or a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bsetw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: or a0, a1, a0
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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@ -166,12 +187,16 @@ define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbset_i32_no_mask:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bsetw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: or a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i32_no_mask:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bsetw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: or a0, a1, a0
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; RV64IBS-NEXT: ret
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%shl = shl i32 1, %b
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%or = or i32 %shl, %a
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@ -191,13 +216,19 @@ define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
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; RV64IB-LABEL: sbset_i32_load:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: bsetw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: or a0, a1, a0
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; RV64IB-NEXT: sext.w a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i32_load:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: lw a0, 0(a0)
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; RV64IBS-NEXT: bsetw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: or a0, a1, a0
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; RV64IBS-NEXT: sext.w a0, a0
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; RV64IBS-NEXT: ret
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%a = load i32, i32* %p
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%shl = shl i32 1, %b
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@ -215,12 +246,14 @@ define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
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;
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; RV64IB-LABEL: sbset_i32_zero:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bsetw a0, zero, a0
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; RV64IB-NEXT: addi a1, zero, 1
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; RV64IB-NEXT: sllw a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i32_zero:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bsetw a0, zero, a0
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; RV64IBS-NEXT: addi a1, zero, 1
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; RV64IBS-NEXT: sllw a0, a1, a0
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; RV64IBS-NEXT: ret
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%shl = shl i32 1, %a
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ret i32 %shl
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@ -302,12 +335,16 @@ define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbinv_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: binvw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: xor a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbinv_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: binvw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: xor a0, a1, a0
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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@ -325,12 +362,16 @@ define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbinv_i32_no_mask:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: binvw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: xor a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbinv_i32_no_mask:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: binvw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: xor a0, a1, a0
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; RV64IBS-NEXT: ret
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%shl = shl i32 1, %b
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%xor = xor i32 %shl, %a
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@ -350,13 +391,19 @@ define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
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; RV64IB-LABEL: sbinv_i32_load:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: binvw a0, a0, a1
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; RV64IB-NEXT: addi a2, zero, 1
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; RV64IB-NEXT: sllw a1, a2, a1
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; RV64IB-NEXT: xor a0, a1, a0
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; RV64IB-NEXT: sext.w a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbinv_i32_load:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: lw a0, 0(a0)
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; RV64IBS-NEXT: binvw a0, a0, a1
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; RV64IBS-NEXT: addi a2, zero, 1
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; RV64IBS-NEXT: sllw a1, a2, a1
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; RV64IBS-NEXT: xor a0, a1, a0
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; RV64IBS-NEXT: sext.w a0, a0
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; RV64IBS-NEXT: ret
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%a = load i32, i32* %p
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%shl = shl i32 1, %b
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@ -418,12 +465,14 @@ define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbext_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bextw a0, a0, a1
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; RV64IB-NEXT: srlw a0, a0, a1
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; RV64IB-NEXT: andi a0, a0, 1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbext_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bextw a0, a0, a1
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; RV64IBS-NEXT: srlw a0, a0, a1
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; RV64IBS-NEXT: andi a0, a0, 1
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shr = lshr i32 %a, %and
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@ -440,12 +489,14 @@ define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
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;
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; RV64IB-LABEL: sbext_i32_no_mask:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bextw a0, a0, a1
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; RV64IB-NEXT: srlw a0, a0, a1
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; RV64IB-NEXT: andi a0, a0, 1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbext_i32_no_mask:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bextw a0, a0, a1
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; RV64IBS-NEXT: srlw a0, a0, a1
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; RV64IBS-NEXT: andi a0, a0, 1
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; RV64IBS-NEXT: ret
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%shr = lshr i32 %a, %b
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%and1 = and i32 %shr, 1
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@ -566,12 +617,12 @@ define signext i32 @sbclri_i32_11(i32 signext %a) nounwind {
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;
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; RV64IB-LABEL: sbclri_i32_11:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bclriw a0, a0, 11
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; RV64IB-NEXT: bclri a0, a0, 11
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclri_i32_11:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: bclriw a0, a0, 11
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; RV64IBS-NEXT: bclri a0, a0, 11
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; RV64IBS-NEXT: ret
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%and = and i32 %a, -2049
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ret i32 %and
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@ -587,12 +638,12 @@ define signext i32 @sbclri_i32_30(i32 signext %a) nounwind {
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;
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; RV64IB-LABEL: sbclri_i32_30:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bclriw a0, a0, 30
|
||||
; RV64IB-NEXT: bclri a0, a0, 30
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbclri_i32_30:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: bclriw a0, a0, 30
|
||||
; RV64IBS-NEXT: bclri a0, a0, 30
|
||||
; RV64IBS-NEXT: ret
|
||||
%and = and i32 %a, -1073741825
|
||||
ret i32 %and
|
||||
@ -608,12 +659,16 @@ define signext i32 @sbclri_i32_31(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbclri_i32_31:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bclriw a0, a0, 31
|
||||
; RV64IB-NEXT: lui a1, 524288
|
||||
; RV64IB-NEXT: addiw a1, a1, -1
|
||||
; RV64IB-NEXT: and a0, a0, a1
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbclri_i32_31:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: bclriw a0, a0, 31
|
||||
; RV64IBS-NEXT: lui a1, 524288
|
||||
; RV64IBS-NEXT: addiw a1, a1, -1
|
||||
; RV64IBS-NEXT: and a0, a0, a1
|
||||
; RV64IBS-NEXT: ret
|
||||
%and = and i32 %a, -2147483649
|
||||
ret i32 %and
|
||||
@ -775,12 +830,12 @@ define signext i32 @sbseti_i32_11(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbseti_i32_11:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bsetiw a0, a0, 11
|
||||
; RV64IB-NEXT: bseti a0, a0, 11
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbseti_i32_11:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: bsetiw a0, a0, 11
|
||||
; RV64IBS-NEXT: bseti a0, a0, 11
|
||||
; RV64IBS-NEXT: ret
|
||||
%or = or i32 %a, 2048
|
||||
ret i32 %or
|
||||
@ -795,12 +850,12 @@ define signext i32 @sbseti_i32_30(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbseti_i32_30:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bsetiw a0, a0, 30
|
||||
; RV64IB-NEXT: bseti a0, a0, 30
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbseti_i32_30:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: bsetiw a0, a0, 30
|
||||
; RV64IBS-NEXT: bseti a0, a0, 30
|
||||
; RV64IBS-NEXT: ret
|
||||
%or = or i32 %a, 1073741824
|
||||
ret i32 %or
|
||||
@ -815,12 +870,14 @@ define signext i32 @sbseti_i32_31(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbseti_i32_31:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: bsetiw a0, a0, 31
|
||||
; RV64IB-NEXT: lui a1, 524288
|
||||
; RV64IB-NEXT: or a0, a0, a1
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbseti_i32_31:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: bsetiw a0, a0, 31
|
||||
; RV64IBS-NEXT: lui a1, 524288
|
||||
; RV64IBS-NEXT: or a0, a0, a1
|
||||
; RV64IBS-NEXT: ret
|
||||
%or = or i32 %a, 2147483648
|
||||
ret i32 %or
|
||||
@ -978,12 +1035,12 @@ define signext i32 @sbinvi_i32_11(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbinvi_i32_11:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: binviw a0, a0, 11
|
||||
; RV64IB-NEXT: binvi a0, a0, 11
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbinvi_i32_11:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: binviw a0, a0, 11
|
||||
; RV64IBS-NEXT: binvi a0, a0, 11
|
||||
; RV64IBS-NEXT: ret
|
||||
%xor = xor i32 %a, 2048
|
||||
ret i32 %xor
|
||||
@ -998,12 +1055,12 @@ define signext i32 @sbinvi_i32_30(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbinvi_i32_30:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: binviw a0, a0, 30
|
||||
; RV64IB-NEXT: binvi a0, a0, 30
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbinvi_i32_30:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: binviw a0, a0, 30
|
||||
; RV64IBS-NEXT: binvi a0, a0, 30
|
||||
; RV64IBS-NEXT: ret
|
||||
%xor = xor i32 %a, 1073741824
|
||||
ret i32 %xor
|
||||
@ -1018,12 +1075,14 @@ define signext i32 @sbinvi_i32_31(i32 signext %a) nounwind {
|
||||
;
|
||||
; RV64IB-LABEL: sbinvi_i32_31:
|
||||
; RV64IB: # %bb.0:
|
||||
; RV64IB-NEXT: binviw a0, a0, 31
|
||||
; RV64IB-NEXT: lui a1, 524288
|
||||
; RV64IB-NEXT: xor a0, a0, a1
|
||||
; RV64IB-NEXT: ret
|
||||
;
|
||||
; RV64IBS-LABEL: sbinvi_i32_31:
|
||||
; RV64IBS: # %bb.0:
|
||||
; RV64IBS-NEXT: binviw a0, a0, 31
|
||||
; RV64IBS-NEXT: lui a1, 524288
|
||||
; RV64IBS-NEXT: xor a0, a0, a1
|
||||
; RV64IBS-NEXT: ret
|
||||
%xor = xor i32 %a, 2147483648
|
||||
ret i32 %xor
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user