RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[DAG] Teach findBaseOffset to interpret indexes of indexed memory operations

Browse Source 
Indexed outputs are addition / subtractions and can be interpreted as such.

llvm-svn: 323539
This commit is contained in:
Nirav Dave 2018-01-26 16:51:27 +00:00
parent 72ddafbbfa
commit 1d49de0371
3 changed files with 37 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
View File

@ -99,16 +99,43 @@ BaseIndexOffset BaseIndexOffset::match(LSBaseSDNode *N,
}
// Consume constant adds & ors with appropriate masking.
while (Base->getOpcode() == ISD::ADD || Base->getOpcode() == ISD::OR) {
if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1))) {
while (true) {
switch (Base->getOpcode()) {
case ISD::OR:
// Only consider ORs which act as adds.
if (Base->getOpcode() == ISD::OR &&
!DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue()))
break;
Offset += C->getSExtValue();
Base = Base->getOperand(0);
continue;
if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1)))
if (DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue())) {
Offset += C->getSExtValue();
Base = Base->getOperand(0);
continue;
}
break;
case ISD::ADD:
if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1))) {
Offset += C->getSExtValue();
Base = Base->getOperand(0);
continue;
}
break;
case ISD::LOAD:
case ISD::STORE: {
auto *LSBase = cast<LSBaseSDNode>(Base.getNode());
unsigned int IndexResNo = (Base->getOpcode() == ISD::LOAD) ? 1 : 0;
if (LSBase->isIndexed() && Base.getResNo() == IndexResNo)
if (auto *C = dyn_cast<ConstantSDNode>(LSBase->getOffset())) {
auto Off = C->getSExtValue();
if (LSBase->getAddressingMode() == ISD::PRE_DEC ||
LSBase->getAddressingMode() == ISD::POST_DEC)
Offset -= Off;
else
Offset += Off;
Base = LSBase->getBasePtr();
continue;
}
break;
}
}
// If we get here break out of the loop.
break;
}

3
test/CodeGen/AArch64/arm64-abi-varargs.ll
View File

@ -13,9 +13,8 @@ define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7,
; CHECK: ldr {{w[0-9]+}}, [sp, #72]
; Second vararg
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #8
; Third vararg
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4

3
test/CodeGen/AArch64/swifterror.ll
View File

@ -316,12 +316,11 @@ define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
; First vararg
; CHECK-APPLE-DAG: orr {{x[0-9]+}}, [[ARGS]], #0x8
; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{.*}}[[TMP]], #16]
; CHECK-APPLE-DAG: add {{x[0-9]+}}, {{x[0-9]+}}, #8
; Second vararg
; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8
; CHECK-APPLE-DAG: add {{x[0-9]+}}, {{x[0-9]+}}, #16
; Third vararg
; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8
; CHECK-APPLE: mov x21, x0
; CHECK-APPLE-NOT: x21