RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 13:11:39 +01:00
Code Issues Projects Releases Wiki Activity

[X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.

Browse Source 
Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel.

llvm-svn: 331645
This commit is contained in:
Simon Pilgrim 2018-05-07 16:34:26 +00:00
parent 0c82ff5aae
commit 1d593b6bcf
3 changed files with 28 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
lib/Target/X86/X86ScheduleZnver1.td
View File

@ -223,14 +223,14 @@ defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFShuffleY, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFVarShuffleY,[ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU0], 5>;
defm : ZnWriteResFpuPair<WriteFMulY, [ZnFPU0], 5>;
defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU01], 3, [1], 1, 7, 1>;
defm : ZnWriteResFpuPair<WriteFMulY, [ZnFPU01], 4, [1], 1, 7, 1>;
defm : ZnWriteResFpuPair<WriteFMA, [ZnFPU03], 5>;
defm : ZnWriteResFpuPair<WriteFMAX, [ZnFPU03], 5>;
defm : ZnWriteResFpuPair<WriteFMAY, [ZnFPU03], 5>;
defm : ZnWriteResFpuPair<WriteFRcp, [ZnFPU01], 5>;
defm : ZnWriteResFpuPair<WriteFRcpX, [ZnFPU01], 5>;
//defm : ZnWriteResFpuPair<WriteFRcpY, [ZnFPU01], 5, [1], 1, 7, 1>;
defm : ZnWriteResFpuPair<WriteFRcpY, [ZnFPU01], 5, [1], 1, 7, 2>;
//defm : ZnWriteResFpuPair<WriteFRsqrt, [ZnFPU02], 5>;
defm : ZnWriteResFpuPair<WriteFRsqrtX, [ZnFPU01], 5, [1], 1, 7, 1>;
//defm : ZnWriteResFpuPair<WriteFRsqrtY, [ZnFPU01], 5, [2], 2>;
@ -1460,32 +1460,6 @@ def : SchedAlias<WriteFHAddLd, ZnWriteMicrocoded>;
def : SchedAlias<WriteFHAddY, ZnWriteMicrocoded>;
def : SchedAlias<WriteFHAddYLd, ZnWriteMicrocoded>;
// MULL SS/SD PS/PD.
// x,x / v,v,v.
def ZnWriteMULr : SchedWriteRes<[ZnFPU01]> {
let Latency = 3;
}
// ymm.
def ZnWriteMULYr : SchedWriteRes<[ZnFPU01]> {
let Latency = 4;
}
def : InstRW<[ZnWriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>;
def : InstRW<[ZnWriteMULYr], (instregex "(V?)MUL(P|S)(S|D)Yrr")>;
// x,m / v,v,m.
def ZnWriteMULLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 10;
let NumMicroOps = 2;
}
def : InstRW<[ZnWriteMULLd], (instregex "(V?)MUL(P|S)(S|D)rm")>;
// ymm
def ZnWriteMULYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 11;
let NumMicroOps = 2;
}
def : InstRW<[ZnWriteMULYLd], (instregex "(V?)MUL(P|S)(S|D)Yrm")>;
// VDIVPS.
// TODO - convert to ZnWriteResFpuPair
// y,y,y.
@ -1520,21 +1494,6 @@ def ZnWriteVDIVPDYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
}
def : SchedAlias<WriteFDiv64YLd, ZnWriteVDIVPDYLd>;
// VRCPPS.
// TODO - convert to ZnWriteResFpuPair
// y,y.
def ZnWriteVRCPPSYr : SchedWriteRes<[ZnFPU01]> {
let Latency = 5;
}
def : SchedAlias<WriteFRcpY, ZnWriteVRCPPSYr>;
// y,m256.
def ZnWriteVRCPPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let Latency = 12;
let NumMicroOps = 3;
}
def : SchedAlias<WriteFRcpYLd, ZnWriteVRCPPSYLd>;
// DPPS.
// x,x,i / v,v,v,i.
def : SchedAlias<WriteDPPS, ZnWriteMicrocoded>;

16
test/CodeGen/X86/x87-schedule.ll
View File

@ -3067,10 +3067,10 @@ define void @test_fmul(float *%a0, double *%a1) optsize {
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: fmul %st(0), %st(1) # sched: [5:1.00]
; ZNVER1-NEXT: fmul %st(2) # sched: [5:1.00]
; ZNVER1-NEXT: fmuls (%ecx) # sched: [12:1.00]
; ZNVER1-NEXT: fmull (%eax) # sched: [12:1.00]
; ZNVER1-NEXT: fmul %st(0), %st(1) # sched: [3:0.50]
; ZNVER1-NEXT: fmul %st(2) # sched: [3:0.50]
; ZNVER1-NEXT: fmuls (%ecx) # sched: [10:0.50]
; ZNVER1-NEXT: fmull (%eax) # sched: [10:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm sideeffect "fmul %st(0), %st(1) \0A\09 fmul %st(2), %st(0) \0A\09 fmuls $0 \0A\09 fmull $1", "*m,*m"(float *%a0, double *%a1) nounwind
@ -3191,10 +3191,10 @@ define void @test_fmulp_fimul(i16 *%a0, i32 *%a1) optsize {
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %eax # sched: [8:0.50]
; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50]
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: fmulp %st(1) # sched: [5:1.00]
; ZNVER1-NEXT: fmulp %st(2) # sched: [5:1.00]
; ZNVER1-NEXT: fimuls (%ecx) # sched: [12:1.00]
; ZNVER1-NEXT: fimull (%eax) # sched: [12:1.00]
; ZNVER1-NEXT: fmulp %st(1) # sched: [3:0.50]
; ZNVER1-NEXT: fmulp %st(2) # sched: [3:0.50]
; ZNVER1-NEXT: fimuls (%ecx) # sched: [10:0.50]
; ZNVER1-NEXT: fimull (%eax) # sched: [10:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
tail call void asm sideeffect "fmulp \0A\09 fmulp %st(2), %st(0) \0A\09 fimuls $0 \0A\09 fimull $1", "*m,*m"(i16 *%a0, i32 *%a1) nounwind

34
test/tools/llvm-mca/X86/Znver1/resources-x87.s
View File

@ -288,14 +288,14 @@ fyl2xp1
# CHECK-NEXT: 1 11 1.00 * fldln2
# CHECK-NEXT: 1 11 1.00 * fldpi
# CHECK-NEXT: 1 8 0.50 * fldz
# CHECK-NEXT: 1 5 1.00 * fmul %st(0), %st(1)
# CHECK-NEXT: 1 5 1.00 * fmul %st(2)
# CHECK-NEXT: 1 12 1.00 * * fmuls (%ecx)
# CHECK-NEXT: 1 12 1.00 * * fmull (%eax)
# CHECK-NEXT: 1 5 1.00 * fmulp %st(1)
# CHECK-NEXT: 1 5 1.00 * fmulp %st(2)
# CHECK-NEXT: 1 12 1.00 * * fimuls (%ecx)
# CHECK-NEXT: 1 12 1.00 * * fimull (%eax)
# CHECK-NEXT: 1 3 0.50 * fmul %st(0), %st(1)
# CHECK-NEXT: 1 3 0.50 * fmul %st(2)
# CHECK-NEXT: 2 10 0.50 * * fmuls (%ecx)
# CHECK-NEXT: 2 10 0.50 * * fmull (%eax)
# CHECK-NEXT: 1 3 0.50 * fmulp %st(1)
# CHECK-NEXT: 1 3 0.50 * fmulp %st(2)
# CHECK-NEXT: 2 10 0.50 * * fimuls (%ecx)
# CHECK-NEXT: 2 10 0.50 * * fimull (%eax)
# CHECK-NEXT: 1 1 1.00 * fnop
# CHECK-NEXT: 1 100 - * fpatan
# CHECK-NEXT: 1 100 - * fprem
@ -371,7 +371,7 @@ fyl2xp1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
# CHECK-NEXT: 32.50 32.50 - - - - - 58.50 2.00 8.00 64.50 -
# CHECK-NEXT: 32.50 32.50 - - - - - 54.50 6.00 8.00 64.50 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
@ -457,14 +457,14 @@ fyl2xp1
# CHECK-NEXT: 0.50 0.50 - - - - - - - - 1.00 - fldln2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - 1.00 - fldpi
# CHECK-NEXT: 0.50 0.50 - - - - - - 0.50 - 0.50 - fldz
# CHECK-NEXT: - - - - - - - 1.00 - - - - fmul %st(0), %st(1)
# CHECK-NEXT: - - - - - - - 1.00 - - - - fmul %st(2)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fmuls (%ecx)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fmull (%eax)
# CHECK-NEXT: - - - - - - - 1.00 - - - - fmulp %st(1)
# CHECK-NEXT: - - - - - - - 1.00 - - - - fmulp %st(2)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fimuls (%ecx)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - fimull (%eax)
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmul %st(0), %st(1)
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmul %st(2)
# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fmuls (%ecx)
# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fmull (%eax)
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmulp %st(1)
# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - fmulp %st(2)
# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fimuls (%ecx)
# CHECK-NEXT: 0.50 0.50 - - - - - 0.50 0.50 - - - fimull (%eax)
# CHECK-NEXT: - - - - - - - 1.00 - - - - fnop
# CHECK-NEXT: - - - - - - - - - - - - fpatan
# CHECK-NEXT: - - - - - - - - - - - - fprem