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[NFC][SVE] Add tests for inserting subvectors into illegal scalable vectors
A previous commit fixed some issues with inserting subvectors into illegal scalable vectors: 0035decae7ab9ab1c988fdcede46598540afd1a0 I've created a patch that simply adds some of those same tests for SVE. Differential Revision: https://reviews.llvm.org/D100641
This commit is contained in:
David Sherwood
parent
a2abff40c5
commit
1d6ba88234
@ -129,7 +129,127 @@ define <vscale x 16 x i8> @insert_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec, <1
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ret <vscale x 16 x i8> %retval
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}
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; Insert subvectors into illegal vectors
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define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl]
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; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl]
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z3.d }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #6, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #4, mul vl]
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-4
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q1, [sp, #32]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x8, #2, mul vl]
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; CHECK-NEXT: ld1d { z2.d }, p0/z, [x8, #3, mul vl]
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; CHECK-NEXT: ld1d { z3.d }, p0/z, [sp]
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; CHECK-NEXT: st1d { z2.d }, p0, [x0, #3, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: st1d { z3.d }, p0, [x0]
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; CHECK-NEXT: addvl sp, sp, #4
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64_lo0(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%sv = load <2 x i64>, <2 x i64>* %psv
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
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; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-2
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: str q0, [sp, #16]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [sp]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1, #1, mul vl]
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; CHECK-NEXT: st1d { z1.d }, p0, [x1]
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; CHECK-NEXT: addvl sp, sp, #2
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%sv = load <2 x i64>, <2 x i64>* %psv
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%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
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store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
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ret void
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}
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declare <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.v2i64(<vscale x 2 x i64>, <2 x i64>, i64)
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declare <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64)
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declare <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.v8i16(<vscale x 8 x i16>, <8 x i16>, i64)
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declare <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8>, <16 x i8>, i64)
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declare <vscale x 16 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
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declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
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