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[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0

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Add unordered indexed load: vluxei

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95028
This commit is contained in:
ShihPo Hung 2021-01-19 01:07:34 -08:00
parent 8009ef0a5f
commit 1d80f86c9c
4 changed files with 10045 additions and 3 deletions
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7
include/llvm/IR/IntrinsicsRISCV.td
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@ -710,9 +710,10 @@ let TargetPrefix = "riscv" in {
defm vse : RISCVUSStore;
defm vlse: RISCVSLoad;
defm vsse: RISCVSStore;
defm vloxei: RISCVILoad;
defm vsoxei: RISCVIStore;
defm vsuxei: RISCVIStore;
defm vluxei : RISCVILoad;
defm vloxei : RISCVILoad;
defm vsoxei : RISCVIStore;
defm vsuxei : RISCVIStore;
defm vamoswap : RISCVAMO;
defm vamoadd : RISCVAMO;

5
lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -2944,6 +2944,7 @@ foreach eew = EEWList in {
// Vector Indexed Loads and Stores
foreach eew = EEWList in {
defm PseudoVLUXEI # eew : VPseudoILoad;
defm PseudoVLOXEI # eew : VPseudoILoad;
defm PseudoVSOXEI # eew : VPseudoIStore;
defm PseudoVSUXEI # eew : VPseudoIStore;
@ -3517,6 +3518,10 @@ foreach eew = EEWList in {
defvar elmul =!cast<LMULInfo>("V_" # elmul_str);
defvar idx_vti = !cast<VTypeInfo>("VI" # eew # elmul_str);
defm : VPatILoad<"int_riscv_vluxei",
"PseudoVLUXEI"#eew,
vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,
vlmul, elmul, vti.RegClass, idx_vti.RegClass>;
defm : VPatILoad<"int_riscv_vloxei",
"PseudoVLOXEI"#eew,
vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,

4138
test/CodeGen/RISCV/rvv/vluxei-rv32.ll Normal file
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5898
test/CodeGen/RISCV/rvv/vluxei-rv64.ll Normal file
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