mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
llvm-svn: 133494
This commit is contained in:
Akira Hatanaka
parent
54d7d72c94
commit
1e08980a21
@ -56,6 +56,9 @@ namespace {
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
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void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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@ -304,6 +307,19 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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return false;
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}
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bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isReg() && "unexpected inline asm memory operand");
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O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")";
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return false;
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}
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void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(opNum);
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@ -94,6 +94,10 @@ private:
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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};
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}
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@ -462,6 +466,14 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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return ResNode;
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}
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bool MipsDAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
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OutOps.push_back(Op);
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return false;
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}
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/// createMipsISelDag - This pass converts a legalized DAG into a
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/// MIPS-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
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@ -59,6 +59,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
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case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
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case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
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case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
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default: return NULL;
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}
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}
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@ -1189,9 +1190,10 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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SDValue MipsTargetLowering::
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LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
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{
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unsigned StackAlignment =
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getTargetMachine().getFrameLowering()->getStackAlignment();
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assert(StackAlignment >=
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MachineFunction &MF = DAG.getMachineFunction();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
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cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
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"Cannot lower if the alignment of the allocated space is larger than \
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that of the stack.");
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@ -1211,24 +1213,14 @@ LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
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// must be placed in the stack pointer register.
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Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
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SDValue());
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// Retrieve updated $sp. There is a glue input to prevent instructions that
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// clobber $sp from being inserted between copytoreg and copyfromreg.
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SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32,
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Chain.getValue(1));
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// The stack space reserved by alloca is located right above the argument
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// area. It is aligned on a boundary that is a multiple of StackAlignment.
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MachineFunction &MF = DAG.getMachineFunction();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) /
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StackAlignment * StackAlignment;
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SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
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DAG.getConstant(SPOffset, MVT::i32));
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// This node always has two return values: a new stack pointer
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// value and a chain
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SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) };
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return DAG.getMergeValues(Ops, 2, dl);
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SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
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SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
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SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
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return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
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}
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SDValue MipsTargetLowering::
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@ -1770,6 +1762,10 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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if (IsPIC && !MipsFI->getGPFI())
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MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
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// Get the frame index of the stack frame object that points to the location
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// of dynamically allocated area on the stack.
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int DynAllocFI = MipsFI->getDynAllocFI();
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// Update size of the maximum argument space.
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// For O32, a minimum of four words (16 bytes) of argument space is
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// allocated.
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@ -1781,14 +1777,17 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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if (MaxCallFrameSize < NextStackOffset) {
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MipsFI->setMaxCallFrameSize(NextStackOffset);
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if (IsPIC) {
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// $gp restore slot must be aligned.
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unsigned StackAlignment = TFL->getStackAlignment();
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NextStackOffset = (NextStackOffset + StackAlignment - 1) /
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StackAlignment * StackAlignment;
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int GPFI = MipsFI->getGPFI();
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MFI->setObjectOffset(GPFI, NextStackOffset);
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}
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// Set the offsets relative to $sp of the $gp restore slot and dynamically
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// allocated stack space. These offsets must be aligned to a boundary
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// determined by the stack alignment of the ABI.
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unsigned StackAlignment = TFL->getStackAlignment();
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NextStackOffset = (NextStackOffset + StackAlignment - 1) /
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StackAlignment * StackAlignment;
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if (IsPIC)
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MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
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MFI->setObjectOffset(DynAllocFI, NextStackOffset);
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}
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// With EABI is it possible to have 16 args on registers.
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@ -79,7 +79,9 @@ namespace llvm {
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BuildPairF64,
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ExtractElementF64,
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WrapperPIC
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WrapperPIC,
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DynAlloc
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};
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}
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@ -39,6 +39,9 @@ def SDT_MipsDivRem : SDTypeProfile<0, 2,
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
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SDTCisVT<1, iPTR>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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@ -99,6 +102,10 @@ def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
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// Pointer to dynamically allocated stack area.
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def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
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[SDNPHasChain, SDNPInGlue]>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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@ -675,6 +682,12 @@ let addr=0 in
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// can be matched. It's similar to Sparc LEA_ADDRi
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def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
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// DynAlloc node points to dynamically allocated stack space.
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// $sp is added to the list of implicitly used registers to prevent dead code
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// elimination from removing instructions that modify $sp.
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let Uses = [SP] in
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def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
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// MADD*/MSUB*
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def MADD : MArithR<0, "madd", MipsMAdd, 1>;
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def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
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@ -852,6 +865,9 @@ def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
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def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
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(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
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// select MipsDynAlloc
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def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//===----------------------------------------------------------------------===//
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@ -27,6 +27,7 @@ namespace llvm {
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class MipsFunctionInfo : public MachineFunctionInfo {
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private:
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MachineFunction& MF;
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/// SRetReturnReg - Some subtargets require that sret lowering includes
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/// returning the value of the returned struct in a register. This field
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/// holds the virtual register into which the sret argument is passed.
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@ -47,6 +48,7 @@ private:
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// LowerCall except for the frame object for restoring $gp.
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std::pair<int, int> InArgFIRange, OutArgFIRange;
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int GPFI; // Index of the frame object for restoring $gp
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mutable int DynAllocFI; // Frame index of dynamically allocated stack area.
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unsigned MaxCallFrameSize;
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/// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap
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@ -55,10 +57,10 @@ private:
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int AtomicFrameIndex;
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public:
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MipsFunctionInfo(MachineFunction& MF)
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: SRetReturnReg(0), GlobalBaseReg(0),
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
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VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
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OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0),
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AtomicFrameIndex(-1)
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OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0),
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MaxCallFrameSize(0), AtomicFrameIndex(-1)
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{}
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bool isInArgFI(int FI) const {
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@ -81,6 +83,16 @@ public:
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bool needGPSaveRestore() const { return getGPFI(); }
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bool isGPFI(int FI) const { return GPFI && GPFI == FI; }
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// The first call to this function creates a frame object for dynamically
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// allocated stack area.
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int getDynAllocFI() const {
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if (!DynAllocFI)
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DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true);
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return DynAllocFI;
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}
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bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; }
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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@ -179,12 +179,14 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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int Offset;
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// Calculate final offset.
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// - There is no need to change the offset if the frame object is an outgoing
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// argument or a $gp restore location,
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// - There is no need to change the offset if the frame object is one of the
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// following: an outgoing argument, pointer to a dynamically allocated
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// stack space or a $gp restore location,
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// - If the frame object is any of the following, its offset must be adjusted
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex))
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
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MipsFI->isDynAllocFI(FrameIndex))
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Offset = spOffset;
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else
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Offset = spOffset + stackSize;
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@ -213,7 +215,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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// 3. Locations for callee-saved registers.
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// Everything else is referenced relative to whatever register
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// getFrameRegister() returns.
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if (MipsFI->isOutArgFI(FrameIndex) ||
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
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(FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
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FrameReg = Mips::SP;
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else
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@ -4,15 +4,15 @@ define i32 @twoalloca(i32 %size) nounwind {
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entry:
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; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
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; CHECK: addu $sp, $zero, $[[T0]]
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; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp
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; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]]
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; CHECK: addu $sp, $zero, $[[T1]]
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; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp
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; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]]
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; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
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; CHECK: addu $sp, $zero, $[[T2]]
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; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
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; CHECK: lw $25, %call16(foo)($gp)
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; CHECK: addiu $4, $[[SP1]], 24
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; CHECK: addu $4, $zero, $[[T1]]
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; CHECK: jalr $25
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; CHECK: lw $25, %call16(foo)($gp)
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; CHECK: addiu $4, $[[SP2]], 24
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; CHECK: addu $4, $zero, $[[T3]]
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; CHECK: jalr $25
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%tmp1 = alloca i8, i32 %size, align 4
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%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
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@ -29,3 +29,72 @@ declare void @foo2(double, double, i32)
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declare i32 @foo(i8*)
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@.str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1
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define i32 @alloca2(i32 %size) nounwind {
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entry:
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; dynamic allocated stack area and $gp restore slot have the same offsets
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; relative to $sp.
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;
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; CHECK: alloca2
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; CHECK: .cprestore [[OFF:[0-9]+]]
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; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
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; CHECK: addu $sp, $zero, $[[T0]]
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; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
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%tmp1 = alloca i8, i32 %size, align 4
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%0 = bitcast i8* %tmp1 to i32*
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%cmp = icmp sgt i32 %size, 10
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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; CHECK: addiu $4, $[[T1]], 40
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%add.ptr = getelementptr inbounds i8* %tmp1, i32 40
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%1 = bitcast i8* %add.ptr to i32*
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call void @foo3(i32* %1) nounwind
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%arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12
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%.pre = bitcast i8* %arrayidx15.pre to i32*
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br label %if.end
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if.else: ; preds = %entry
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; CHECK: addiu $4, $[[T1]], 12
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%add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12
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%2 = bitcast i8* %add.ptr5 to i32*
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call void @foo3(i32* %2) nounwind
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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; CHECK: lw $5, 0($[[T1]])
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; CHECK: lw $25, %call16(printf)
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%.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ]
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%tmp7 = load i32* %0, align 4, !tbaa !0
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%arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4
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%3 = bitcast i8* %arrayidx9 to i32*
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%tmp10 = load i32* %3, align 4, !tbaa !0
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%arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8
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%4 = bitcast i8* %arrayidx12 to i32*
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%tmp13 = load i32* %4, align 4, !tbaa !0
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%tmp16 = load i32* %.pre-phi, align 4, !tbaa !0
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%arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16
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%5 = bitcast i8* %arrayidx18 to i32*
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%tmp19 = load i32* %5, align 4, !tbaa !0
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%arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20
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%6 = bitcast i8* %arrayidx21 to i32*
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%tmp22 = load i32* %6, align 4, !tbaa !0
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%arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24
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%7 = bitcast i8* %arrayidx24 to i32*
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%tmp25 = load i32* %7, align 4, !tbaa !0
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%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
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ret i32 0
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}
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declare void @foo3(i32*)
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declare i32 @printf(i8* nocapture, ...) nounwind
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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23
test/CodeGen/Mips/inlineasmmemop.ll
Normal file
23
test/CodeGen/Mips/inlineasmmemop.ll
Normal file
@ -0,0 +1,23 @@
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; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
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@g1 = external global i32
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define i32 @f1(i32 %x) nounwind {
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entry:
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; CHECK: addiu $[[T0:[0-9]+]], $sp
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; CHECK: #APP
|
||||
; CHECK: sw $4, 0($[[T0]])
|
||||
; CHECK: #NO_APP
|
||||
; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
|
||||
; CHECK: #APP
|
||||
; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
|
||||
; CHECK: #NO_APP
|
||||
; CHECK: sw $[[T3]], 0($[[T1]])
|
||||
|
||||
%l1 = alloca i32, align 4
|
||||
call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
|
||||
%0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
|
||||
store i32 %0, i32* @g1, align 4
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user