RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

[x86] Fix PR34377 by disabling cmov conversion when we relied on it

Browse Source 
performing a zext of a register.

On the PR there is discussion of how to more effectively handle this,
but this patch prevents us from miscompiling code.

Differential Revision: https://reviews.llvm.org/D37504

llvm-svn: 312620
This commit is contained in:
Chandler Carruth 2017-09-06 06:28:08 +00:00
parent 1830a8ffe2
commit 1e362133d5
2 changed files with 32 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/X86/X86CmovConversion.cpp
View File

@ -289,6 +289,16 @@ bool X86CmovConverterPass::collectCmovCandidates(
// Can't handle mixed conditions with memory operands.
SkipGroup = true;
}
// Check if we were relying on zero-extending behavior of the CMOV.
if (!SkipGroup &&
llvm::any_of(
MRI->use_nodbg_instructions(I.defs().begin()->getReg()),
[&](MachineInstr &UseI) {
return UseI.getOpcode() == X86::SUBREG_TO_REG;
}))
// FIXME: We should model the cost of using an explicit MOV to handle
// the zero-extension rather than just refusing to handle this.
SkipGroup = true;
continue;
}
// If Group is empty, keep looking for first CMOV in the range.

26
test/CodeGen/X86/cmov-into-branch.ll
View File

@ -61,6 +61,24 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) {
ret i32 %cond5
}
; Zero-extended select.
define void @test6(i32 %a, i32 %x, i32* %y.ptr, i64* %z.ptr) {
; CHECK-LABEL: test6:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: cmovnsl (%rdx), %esi
; CHECK-NEXT: movq %rsi, (%rcx)
; CHECK-NEXT: retq
entry:
%y = load i32, i32* %y.ptr
%cmp = icmp slt i32 %a, 0
%z = select i1 %cmp, i32 %x, i32 %y
%z.ext = zext i32 %z to i64
store i64 %z.ext, i64* %z.ptr
ret void
}
; If a select is not obviously predictable, don't turn it into a branch.
define i32 @weighted_select1(i32 %a, i32 %b) {
; CHECK-LABEL: weighted_select1:
@ -79,10 +97,10 @@ define i32 @weighted_select2(i32 %a, i32 %b) {
; CHECK-LABEL: weighted_select2:
; CHECK: # BB#0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jne .LBB5_2
; CHECK-NEXT: jne .LBB6_2
; CHECK-NEXT: # BB#1: # %select.false
; CHECK-NEXT: movl %esi, %edi
; CHECK-NEXT: .LBB5_2: # %select.end
; CHECK-NEXT: .LBB6_2: # %select.end
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%cmp = icmp ne i32 %a, 0
@ -98,11 +116,11 @@ define i32 @weighted_select3(i32 %a, i32 %b) {
; CHECK-LABEL: weighted_select3:
; CHECK: # BB#0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: je .LBB6_1
; CHECK-NEXT: je .LBB7_1
; CHECK-NEXT: # BB#2: # %select.end
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB6_1: # %select.false
; CHECK-NEXT: .LBB7_1: # %select.false
; CHECK-NEXT: movl %esi, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq