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[WebAssembly] Use target-independent saturating add

Browse Source 
Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53721

llvm-svn: 345299
This commit is contained in:
Thomas Lively 2018-10-25 19:06:13 +00:00
parent a189f00e22
commit 1e39ce25ff
4 changed files with 16 additions and 26 deletions
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8
include/llvm/IR/IntrinsicsWebAssembly.td
View File

@ -102,14 +102,6 @@ def int_wasm_atomic_notify:
// SIMD intrinsics
//===----------------------------------------------------------------------===//
def int_wasm_add_saturate_signed :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_add_saturate_unsigned :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_sub_saturate_signed :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],

6
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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@ -115,6 +115,12 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
setTruncStoreAction(T, MVT::f16, Expand);
}
// Support saturating add for i8x16 and i16x8
if (Subtarget->hasSIMD128())
for (auto T : {MVT::v16i8, MVT::v8i16})
for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
setOperationAction(Op, T, Legal);
for (auto T : {MVT::i32, MVT::i64}) {
// Expand unavailable integer operations.
for (auto Op :

4
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
View File

@ -469,9 +469,9 @@ multiclass SIMDBinarySat<SDNode node, string name, bits<32> baseInst> {
// Saturating integer addition: add_saturate_s / add_saturate_u
let isCommutable = 1 in {
defm ADD_SAT_S :
SIMDBinarySat<int_wasm_add_saturate_signed, "add_saturate_s", 40>;
SIMDBinarySat<saddsat, "add_saturate_s", 40>;
defm ADD_SAT_U :
SIMDBinarySat<int_wasm_add_saturate_unsigned, "add_saturate_u", 41>;
SIMDBinarySat<uaddsat, "add_saturate_u", 41>;
} // isCommutable = 1
// Saturating integer subtraction: sub_saturate_s / sub_saturate_u

24
test/CodeGen/WebAssembly/simd-intrinsics.ll
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@ -16,11 +16,9 @@ target triple = "wasm32-unknown-unknown"
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
%a = call <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(
<16 x i8> %x, <16 x i8> %y
)
%a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %a
}
@ -29,11 +27,9 @@ define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
%a = call <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(
<16 x i8> %x, <16 x i8> %y
)
%a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %a
}
@ -106,11 +102,9 @@ define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
%a = call <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(
<8 x i16> %x, <8 x i16> %y
)
%a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %a
}
@ -119,11 +113,9 @@ define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
%a = call <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(
<8 x i16> %x, <8 x i16> %y
)
%a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %a
}