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[llvm-objcopy] Add RISC-V support for -B/-O
Reviewers: jorgbrown, espindola, alexshap, jhenderson Subscribers: emaste, arichardson, fedor.sergeev, jakehehrlich, kito-cheng, shiva0217, MaskRay, rogfer01, rkruppe, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61272 llvm-svn: 359568
This commit is contained in:
Jordan Rupprecht
parent
eb060c9323
commit
1e69655c25
@ -18,6 +18,12 @@
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# RUN: llvm-objcopy -I binary -B powerpc:common64 %t.txt %t.powerpc_common64.o
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# RUN: llvm-readobj --file-headers %t.powerpc_common64.o | FileCheck %s --check-prefixes=CHECK,LE,PPC,64
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# RUN: llvm-objcopy -I binary -B riscv:rv32 %t.txt %t.rv32.o
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# RUN: llvm-readobj --file-headers %t.rv32.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV32,32
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# RUN: llvm-objcopy -I binary -B riscv:rv64 %t.txt %t.rv64.o
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# RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64
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# RUN: llvm-objcopy -I binary -B sparc %t.txt %t.sparc.o
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# RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,LE,SPARC,32
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@ -25,19 +31,25 @@
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# RUN: llvm-readobj --file-headers %t.x86-64.o | FileCheck %s --check-prefixes=CHECK,LE,X86-64,64
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# CHECK: Format:
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# AARCH64-SAME: ELF64-aarch64-little
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# ARM-SAME: ELF32-arm-little
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# I386-SAME: ELF32-i386
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# MIPS-SAME: ELF32-mips{{$}}
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# PPC-SAME: ELF64-ppc64
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# SPARC-SAME: ELF32-sparc
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# X86-64-SAME: ELF64-x86-64
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# 32-SAME: ELF32-
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# 64-SAME: ELF64-
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# AARCH64-SAME: aarch64-little
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# ARM-SAME: arm-little
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# I386-SAME: i386
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# MIPS-SAME: mips{{$}}
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# RISCV32-SAME: riscv{{$}}
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# RISCV64-SAME: riscv{{$}}
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# PPC-SAME: ppc64
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# SPARC-SAME: sparc
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# X86-64-SAME: x86-64
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# AARCH64-NEXT: Arch: aarch64
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# ARM-NEXT: Arch: arm
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# I386-NEXT: Arch: i386
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# MIPS-NEXT: Arch: mips{{$$}}
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# PPC-NEXT: Arch: powerpc64le
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# RISCV32-NEXT: Arch: riscv32
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# RISCV64-NEXT: Arch: riscv64
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# SPARC-NEXT: Arch: sparcel
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# X86-64-NEXT: Arch: x86_64
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@ -62,6 +74,8 @@
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# I386-NEXT: Machine: EM_386 (0x3)
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# MIPS-NEXT: Machine: EM_MIPS (0x8)
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# PPC-NEXT: Machine: EM_PPC64 (0x15)
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# RISCV32-NEXT: Machine: EM_RISCV (0xF3)
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# RISCV64-NEXT: Machine: EM_RISCV (0xF3)
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# SPARC-NEXT: Machine: EM_SPARC (0x2)
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# X86-64-NEXT: Machine: EM_X86_64 (0x3E)
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# CHECK-NEXT: Version: 1
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@ -53,6 +53,14 @@
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# RUN: llvm-readobj --file-headers %t.elf64_ppcle.o | FileCheck %s --check-prefixes=CHECK,LE,PPC64LE,64,SYSV
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# RUN: llvm-readobj --file-headers %t.elf64_ppcle.dwo | FileCheck %s --check-prefixes=CHECK,LE,PPC64LE,64,SYSV
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# RUN: llvm-objcopy %t.o -O elf32-littleriscv %t.elf32_littleriscv.o --split-dwo=%t.elf32_littleriscv.dwo
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# RUN: llvm-readobj --file-headers %t.elf32_littleriscv.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV32,32,SYSV
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# RUN: llvm-readobj --file-headers %t.elf32_littleriscv.dwo | FileCheck %s --check-prefixes=CHECK,LE,RISCV32,32,SYSV
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# RUN: llvm-objcopy %t.o -O elf64-littleriscv %t.elf64_littleriscv.o --split-dwo=%t.elf64_littleriscv.dwo
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# RUN: llvm-readobj --file-headers %t.elf64_littleriscv.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64,SYSV
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# RUN: llvm-readobj --file-headers %t.elf64_littleriscv.dwo | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64,SYSV
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# RUN: llvm-objcopy %t.o -O elf64-x86-64 %t.elf64_x86_64.o --split-dwo=%t.elf64_x86_64.dwo
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# RUN: llvm-readobj --file-headers %t.elf64_x86_64.o | FileCheck %s --check-prefixes=CHECK,LE,X86-64,64,SYSV
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# RUN: llvm-readobj --file-headers %t.elf64_x86_64.dwo | FileCheck %s --check-prefixes=CHECK,LE,X86-64,64,SYSV
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@ -127,6 +135,8 @@ Symbols:
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# PPC-SAME: ppc{{$}}
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# PPC64BE-SAME: ppc64{{$}}
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# PPC64LE-SAME: ppc64{{$}}
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# RISCV32-SAME: riscv{{$}}
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# RISCV64-SAME: riscv{{$}}
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# X86-64-SAME: x86-64
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# DEFAULT-SAME: unknown
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@ -141,6 +151,8 @@ Symbols:
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# PPC-NEXT: Arch: powerpc{{$}}
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# PPC64BE-NEXT: Arch: powerpc64{{$}}
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# PPC64LE-NEXT: Arch: powerpc64le
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# RISCV32-NEXT: Arch: riscv32
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# RISCV64-NEXT: Arch: riscv64
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# X86-64-NEXT: Arch: x86_64
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# DEFAULT-NEXT: Arch: unknown
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@ -156,14 +168,16 @@ Symbols:
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# FREEBSD: OS/ABI: FreeBSD (0x9)
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# DEFAULT: OS/ABI: Standalone (0xFF)
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# AARCH: Machine: EM_AARCH64 (0xB7)
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# ARM: Machine: EM_ARM (0x28)
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# I386: Machine: EM_386 (0x3)
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# IAMCU: Machine: EM_IAMCU (0x6)
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# MIPS: Machine: EM_MIPS (0x8)
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# PPC: Machine: EM_PPC (0x14)
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# PPC64: Machine: EM_PPC64 (0x15)
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# X86-64: Machine: EM_X86_64 (0x3E)
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# AARCH: Machine: EM_AARCH64 (0xB7)
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# ARM: Machine: EM_ARM (0x28)
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# I386: Machine: EM_386 (0x3)
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# IAMCU: Machine: EM_IAMCU (0x6)
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# MIPS: Machine: EM_MIPS (0x8)
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# PPC: Machine: EM_PPC (0x14)
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# PPC64: Machine: EM_PPC64 (0x15)
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# RISCV32: Machine: EM_RISCV (0xF3)
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# RISCV64: Machine: EM_RISCV (0xF3)
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# X86-64: Machine: EM_X86_64 (0x3E)
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# 32: HeaderSize: 52
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# 64: HeaderSize: 64
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@ -260,6 +260,8 @@ static const StringMap<MachineInfo> ArchMap{
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{"i386:x86-64", {ELF::EM_X86_64, true, true}},
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{"mips", {ELF::EM_MIPS, false, false}},
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{"powerpc:common64", {ELF::EM_PPC64, true, true}},
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{"riscv:rv32", {ELF::EM_RISCV, false, true}},
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{"riscv:rv64", {ELF::EM_RISCV, true, true}},
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{"sparc", {ELF::EM_SPARC, false, true}},
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{"x86-64", {ELF::EM_X86_64, true, true}},
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};
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@ -275,22 +277,31 @@ static Expected<const MachineInfo &> getMachineInfo(StringRef Arch) {
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// FIXME: consolidate with the bfd parsing used by lld.
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static const StringMap<MachineInfo> OutputFormatMap{
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// Name, {EMachine, 64bit, LittleEndian}
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// x86
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{"elf32-i386", {ELF::EM_386, false, true}},
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{"elf32-iamcu", {ELF::EM_IAMCU, false, true}},
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{"elf32-littlearm", {ELF::EM_ARM, false, true}},
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{"elf32-x86-64", {ELF::EM_X86_64, false, true}},
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{"elf64-x86-64", {ELF::EM_X86_64, true, true}},
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// Intel MCU
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{"elf32-iamcu", {ELF::EM_IAMCU, false, true}},
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// ARM
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{"elf32-littlearm", {ELF::EM_ARM, false, true}},
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// ARM AArch64
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{"elf64-aarch64", {ELF::EM_AARCH64, true, true}},
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{"elf64-littleaarch64", {ELF::EM_AARCH64, true, true}},
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// RISC-V
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{"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
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{"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
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// PowerPC
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{"elf32-powerpc", {ELF::EM_PPC, false, false}},
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{"elf32-powerpcle", {ELF::EM_PPC, false, true}},
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{"elf64-powerpc", {ELF::EM_PPC64, true, false}},
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{"elf64-powerpcle", {ELF::EM_PPC64, true, true}},
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{"elf64-x86-64", {ELF::EM_X86_64, true, true}},
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{"elf32-tradbigmips", {ELF::EM_MIPS, false, false}},
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// MIPS
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{"elf32-bigmips", {ELF::EM_MIPS, false, false}},
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{"elf32-ntradbigmips", {ELF::EM_MIPS, false, false}},
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{"elf32-tradlittlemips", {ELF::EM_MIPS, false, true}},
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{"elf32-ntradlittlemips", {ELF::EM_MIPS, false, true}},
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{"elf32-tradbigmips", {ELF::EM_MIPS, false, false}},
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{"elf32-tradlittlemips", {ELF::EM_MIPS, false, true}},
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{"elf64-tradbigmips", {ELF::EM_MIPS, true, false}},
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{"elf64-tradlittlemips", {ELF::EM_MIPS, true, true}},
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};
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