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[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX redux.sync instructions
Adds NVPTX builtins and intrinsics for the CUDA PTX `redux.sync` instructions for `sm_80` architecture or newer. PTX ISA description of `redux.sync`: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-redux-sync Authored-by: Steffen Larsen <steffen.larsen@codeplay.com> Differential Revision: https://reviews.llvm.org/D100124
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@ -4204,6 +4204,49 @@ def int_nvvm_match_all_sync_i64p :
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Intrinsic<[llvm_i64_ty, llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty],
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Intrinsic<[llvm_i64_ty, llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty],
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[IntrInaccessibleMemOnly, IntrConvergent], "llvm.nvvm.match.all.sync.i64p">;
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[IntrInaccessibleMemOnly, IntrConvergent], "llvm.nvvm.match.all.sync.i64p">;
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//
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// REDUX.SYNC
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//
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// redux.sync.min.u32 dst, src, membermask;
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def int_nvvm_redux_sync_umin : GCCBuiltin<"__nvvm_redux_sync_umin">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.max.u32 dst, src, membermask;
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def int_nvvm_redux_sync_umax : GCCBuiltin<"__nvvm_redux_sync_umax">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.add.s32 dst, src, membermask;
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def int_nvvm_redux_sync_add : GCCBuiltin<"__nvvm_redux_sync_add">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.min.s32 dst, src, membermask;
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def int_nvvm_redux_sync_min : GCCBuiltin<"__nvvm_redux_sync_min">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.max.s32 dst, src, membermask;
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def int_nvvm_redux_sync_max : GCCBuiltin<"__nvvm_redux_sync_max">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.and.b32 dst, src, membermask;
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def int_nvvm_redux_sync_and : GCCBuiltin<"__nvvm_redux_sync_and">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.xor.b32 dst, src, membermask;
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def int_nvvm_redux_sync_xor : GCCBuiltin<"__nvvm_redux_sync_xor">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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// redux.sync.or.b32 dst, src, membermask;
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def int_nvvm_redux_sync_or : GCCBuiltin<"__nvvm_redux_sync_or">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly]>;
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//
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//
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// WMMA instructions
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// WMMA instructions
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//
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//
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@ -274,6 +274,22 @@ defm MATCH_ALLP_SYNC_32 : MATCH_ALLP_SYNC<Int32Regs, "b32", int_nvvm_match_all_s
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defm MATCH_ALLP_SYNC_64 : MATCH_ALLP_SYNC<Int64Regs, "b64", int_nvvm_match_all_sync_i64p,
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defm MATCH_ALLP_SYNC_64 : MATCH_ALLP_SYNC<Int64Regs, "b64", int_nvvm_match_all_sync_i64p,
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i64imm>;
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i64imm>;
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multiclass REDUX_SYNC<string BinOp, string PTXType, Intrinsic Intrin> {
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def : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src, Int32Regs:$mask),
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"redux.sync." # BinOp # "." # PTXType # " $dst, $src, $mask;",
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[(set Int32Regs:$dst, (Intrin Int32Regs:$src, Int32Regs:$mask))]>,
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Requires<[hasPTX70, hasSM80]>;
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}
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defm REDUX_SYNC_UMIN : REDUX_SYNC<"min", "u32", int_nvvm_redux_sync_umin>;
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defm REDUX_SYNC_UMAX : REDUX_SYNC<"max", "u32", int_nvvm_redux_sync_umax>;
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defm REDUX_SYNC_ADD : REDUX_SYNC<"add", "s32", int_nvvm_redux_sync_add>;
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defm REDUX_SYNC_MIN : REDUX_SYNC<"min", "s32", int_nvvm_redux_sync_min>;
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defm REDUX_SYNC_MAX : REDUX_SYNC<"max", "s32", int_nvvm_redux_sync_max>;
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defm REDUX_SYNC_AND : REDUX_SYNC<"and", "b32", int_nvvm_redux_sync_and>;
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defm REDUX_SYNC_XOR : REDUX_SYNC<"xor", "b32", int_nvvm_redux_sync_xor>;
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defm REDUX_SYNC_OR : REDUX_SYNC<"or", "b32", int_nvvm_redux_sync_or>;
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} // isConvergent = true
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} // isConvergent = true
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//-----------------------------------
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//-----------------------------------
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65
test/CodeGen/NVPTX/redux-sync.ll
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65
test/CodeGen/NVPTX/redux-sync.ll
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@ -0,0 +1,65 @@
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | FileCheck %s
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declare i32 @llvm.nvvm.redux.sync.umin(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_min_u32
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define i32 @redux_sync_min_u32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.min.u32
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%val = call i32 @llvm.nvvm.redux.sync.umin(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.umax(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_max_u32
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define i32 @redux_sync_max_u32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.max.u32
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%val = call i32 @llvm.nvvm.redux.sync.umax(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.add(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_add_s32
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define i32 @redux_sync_add_s32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.add.s32
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%val = call i32 @llvm.nvvm.redux.sync.add(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.min(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_min_s32
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define i32 @redux_sync_min_s32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.min.s32
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%val = call i32 @llvm.nvvm.redux.sync.min(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.max(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_max_s32
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define i32 @redux_sync_max_s32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.max.s32
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%val = call i32 @llvm.nvvm.redux.sync.max(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.and(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_and_b32
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define i32 @redux_sync_and_b32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.and.b32
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%val = call i32 @llvm.nvvm.redux.sync.and(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.xor(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_xor_b32
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define i32 @redux_sync_xor_b32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.xor.b32
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%val = call i32 @llvm.nvvm.redux.sync.xor(i32 %src, i32 %mask)
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ret i32 %val
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}
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declare i32 @llvm.nvvm.redux.sync.or(i32, i32)
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; CHECK-LABEL: .func{{.*}}redux_sync_or_b32
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define i32 @redux_sync_or_b32(i32 %src, i32 %mask) {
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; CHECK: redux.sync.or.b32
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%val = call i32 @llvm.nvvm.redux.sync.or(i32 %src, i32 %mask)
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ret i32 %val
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}
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