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[SelectionDAG] Support BUILD_VECTOR implicit truncation in SelectionDAG::ComputeNumSignBits (PR32273)

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llvm-svn: 297852
This commit is contained in:
Simon Pilgrim 2017-03-15 16:22:24 +00:00
parent 962a1447c8
commit 1e8a4166d4
2 changed files with 18 additions and 7 deletions
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17
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2906,9 +2906,20 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
}
case ISD::BUILD_VECTOR:
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
for (unsigned i = 1, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i)
Tmp = std::min(Tmp, ComputeNumSignBits(Op.getOperand(i), Depth + 1));
Tmp = VTBits;
for (unsigned i = 0, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
SDValue SrcOp = Op.getOperand(i);
Tmp2 = ComputeNumSignBits(Op.getOperand(i), Depth + 1);
// BUILD_VECTOR can implicitly truncate sources, we must handle this.
if (SrcOp.getValueSizeInBits() != VTBits) {
assert(SrcOp.getValueSizeInBits() > VTBits &&
"Expected BUILD_VECTOR implicit truncation");
unsigned ExtraBits = SrcOp.getValueSizeInBits() - VTBits;
Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
}
Tmp = std::min(Tmp, Tmp2);
}
return Tmp;
case ISD::SIGN_EXTEND:

8
test/CodeGen/AArch64/dag-numsignbits.ll
View File

@ -6,10 +6,10 @@ define void @signbits_vXi1(<4 x i16> %a1) {
; CHECK-LABEL: signbits_vXi1
; CHECK: cmgt v0.4h, v1.4h, v0.4h
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[3]
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: and w3, w9, #0x1
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: sshr v0.4h, v0.4h, #15
; CHECK-NEXT: umov w0, v0.h[0]
; CHECK-NEXT: umov w3, v0.h[3]
; CHECK-NEXT: mov w1, wzr
; CHECK-NEXT: mov w2, wzr
; CHECK-NEXT: b foo