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[x86] Regenerate a bunch more avx512 test cases using my script to have
tighter, more strict FileCheck assertions. Some of these I really like as they show case exactly what instruction sequences come out of these microscopic functionality tests. llvm-svn: 218936
This commit is contained in:
Chandler Carruth
parent
b9f6e47007
commit
1ebea4c8bd
@ -1,30 +1,44 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vpxord
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; CHECK: ret
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define <16 x i32> @test1(i32* %x) {
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; CHECK-LABEL: test1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovd (%rdi), %xmm0
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; CHECK-NEXT: vmovdqa32 {{.*}}(%rip), %zmm1
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; CHECK-NEXT: vpxord %zmm2, %zmm2, %zmm2
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; CHECK-NEXT: vpermt2d %zmm0, %zmm1, %zmm2
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; CHECK-NEXT: vmovdqa32 {{.*}}(%rip), %zmm0
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; CHECK-NEXT: vpermd %zmm2, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%y = load i32* %x, align 4
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%res = insertelement <16 x i32>zeroinitializer, i32 %y, i32 4
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test2
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; CHECK: vpaddd LCP{{.*}}(%rip){1to16}
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; CHECK: ret
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define <16 x i32> @test2(<16 x i32> %x) {
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; CHECK-LABEL: test2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%res = add <16 x i32><i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, %x
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test3
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; CHECK: vinsertf128
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; CHECK: vinsertf64x4
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; CHECK: ret
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define <16 x float> @test3(<4 x float> %a) {
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; CHECK-LABEL: test3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovhlps %xmm0, %xmm0, %xmm1
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; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vmovss %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: vmovss %xmm1, %xmm2, %xmm1
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; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,0],xmm0[0,1]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
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; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1
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; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = extractelement <4 x float> %a, i32 2
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%c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5
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%b1 = extractelement <4 x float> %a, i32 0
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%c1 = insertelement <16 x float> %c, float %b1, i32 6
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ret <16 x float>%c1
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}
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}
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@ -1,60 +1,72 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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;CHECK-LABEL: _inreg16xi32:
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;CHECK: vpbroadcastd {{.*}}, %zmm
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;CHECK: ret
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define <16 x i32> @_inreg16xi32(i32 %a) {
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; CHECK-LABEL: _inreg16xi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpbroadcastd %edi, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <16 x i32> undef, i32 %a, i32 0
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%c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %c
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}
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;CHECK-LABEL: _inreg8xi64:
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;CHECK: vpbroadcastq {{.*}}, %zmm
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;CHECK: ret
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define <8 x i64> @_inreg8xi64(i64 %a) {
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; CHECK-LABEL: _inreg8xi64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpbroadcastq %rdi, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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ret <8 x i64> %c
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}
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;CHECK-LABEL: _inreg16xfloat:
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;CHECK: vbroadcastss {{.*}}, %zmm
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;CHECK: ret
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define <16 x float> @_inreg16xfloat(float %a) {
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; CHECK-LABEL: _inreg16xfloat:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %c
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}
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;CHECK-LABEL: _inreg8xdouble:
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;CHECK: vbroadcastsd {{.*}}, %zmm
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;CHECK: ret
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define <8 x double> @_inreg8xdouble(double %a) {
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; CHECK-LABEL: _inreg8xdouble:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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ret <8 x double> %c
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}
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;CHECK-LABEL: _xmm16xi32
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;CHECK: vpbroadcastd
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;CHECK: ret
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define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
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; CHECK-LABEL: _xmm16xi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpbroadcastd %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %b
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}
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;CHECK-LABEL: _xmm16xfloat
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;CHECK: vbroadcastss {{.*}}
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;CHECK: ret
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define <16 x float> @_xmm16xfloat(<16 x float> %a) {
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; CHECK-LABEL: _xmm16xfloat:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %b
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}
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define <16 x i32> @test_vbroadcast() {
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; CHECK-LABEL: _test_vbroadcast:
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; CHECK: vpbroadcastd
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; CHECK-LABEL: test_vbroadcast:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
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; CHECK-NEXT: vcmpunordps %zmm0, %zmm0, %k1
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; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
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; CHECK-NEXT: knotw %k1, %k1
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; CHECK-NEXT: vmovdqu32 %zmm0, %zmm0 {%k1} {z}
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; CHECK-NEXT: retq
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entry:
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%0 = sext <16 x i1> zeroinitializer to <16 x i32>
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%1 = fcmp uno <16 x float> undef, zeroinitializer
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@ -66,8 +78,10 @@ entry:
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; We implement the set1 intrinsics with vector initializers. Verify that the
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; IR generated will produce broadcasts at the end.
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define <8 x double> @test_set1_pd(double %d) #2 {
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; CHECK-LABEL: _test_set1_pd:
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; CHECK: vbroadcastsd
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; CHECK-LABEL: test_set1_pd:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
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; CHECK-NEXT: retq
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entry:
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%vecinit.i = insertelement <8 x double> undef, double %d, i32 0
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%vecinit1.i = insertelement <8 x double> %vecinit.i, double %d, i32 1
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@ -81,8 +95,10 @@ entry:
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}
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define <8 x i64> @test_set1_epi64(i64 %d) #2 {
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; CHECK-LABEL: _test_set1_epi64:
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; CHECK: vpbroadcastq
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; CHECK-LABEL: test_set1_epi64:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpbroadcastq %rdi, %zmm0
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; CHECK-NEXT: retq
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entry:
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%vecinit.i = insertelement <8 x i64> undef, i64 %d, i32 0
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%vecinit1.i = insertelement <8 x i64> %vecinit.i, i64 %d, i32 1
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@ -96,8 +112,10 @@ entry:
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}
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define <16 x float> @test_set1_ps(float %f) #2 {
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; CHECK-LABEL: _test_set1_ps:
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; CHECK: vbroadcastss
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; CHECK-LABEL: test_set1_ps:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
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; CHECK-NEXT: retq
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entry:
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%vecinit.i = insertelement <16 x float> undef, float %f, i32 0
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%vecinit1.i = insertelement <16 x float> %vecinit.i, float %f, i32 1
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@ -119,8 +137,10 @@ entry:
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}
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define <16 x i32> @test_set1_epi32(i32 %f) #2 {
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; CHECK-LABEL: _test_set1_epi32:
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; CHECK: vpbroadcastd
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; CHECK-LABEL: test_set1_epi32:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpbroadcastd %edi, %zmm0
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; CHECK-NEXT: retq
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entry:
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%vecinit.i = insertelement <16 x i32> undef, i32 %f, i32 0
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%vecinit1.i = insertelement <16 x i32> %vecinit.i, i32 %f, i32 1
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@ -144,8 +164,10 @@ entry:
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; We implement the scalar broadcast intrinsics with vector initializers.
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; Verify that the IR generated will produce the broadcast at the end.
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define <8 x double> @test_mm512_broadcastsd_pd(<2 x double> %a) {
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; CHECK-LABEL: _test_mm512_broadcastsd_pd:
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; CHECK: vbroadcastsd %xmm0, %zmm0
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; CHECK-LABEL: test_mm512_broadcastsd_pd:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = extractelement <2 x double> %a, i32 0
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%vecinit.i = insertelement <8 x double> undef, double %0, i32 0
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@ -1,145 +1,176 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vcmpleps
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; CHECK: vmovaps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcmpleps %zmm1, %zmm0, %k1
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; CHECK-NEXT: vmovaps %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%mask = fcmp ole <16 x float> %x, %y
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%max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %y
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ret <16 x float> %max
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}
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; CHECK-LABEL: test2
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; CHECK: vcmplepd
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; CHECK: vmovapd
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; CHECK: ret
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define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcmplepd %zmm1, %zmm0, %k1
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; CHECK-NEXT: vmovapd %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%mask = fcmp ole <8 x double> %x, %y
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%max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %y
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ret <8 x double> %max
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}
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; CHECK-LABEL: test3
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; CHECK: vpcmpeqd (%rdi)
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpcmpeqd (%rdi), %zmm0, %k1
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; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%y = load <16 x i32>* %yp, align 4
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%mask = icmp eq <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test4_unsigned
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; CHECK: vpcmpnltud
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
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; CHECK-LABEL: test4_unsigned:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpcmpnltud %zmm1, %zmm0, %k1
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; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%mask = icmp uge <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test5
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; CHECK: vpcmpeqq {{.*}}%k1
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
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; CHECK-LABEL: test5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k1
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; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%mask = icmp eq <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test6_unsigned
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; CHECK: vpcmpnleuq {{.*}}%k1
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; CHECK: vmovdqa64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y) nounwind {
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; CHECK-LABEL: test6_unsigned:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpcmpnleuq %zmm1, %zmm0, %k1
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; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%mask = icmp ugt <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test7
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; CHECK: xor
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; CHECK: vcmpltps
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; CHECK: vblendvps
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; CHECK: ret
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define <4 x float> @test7(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test7:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vcmpltps %xmm2, %xmm0, %xmm2
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; CHECK-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: retq
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%mask = fcmp olt <4 x float> %a, zeroinitializer
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%c = select <4 x i1>%mask, <4 x float>%a, <4 x float>%b
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ret <4 x float>%c
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}
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; CHECK-LABEL: test8
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; CHECK: xor
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; CHECK: vcmpltpd
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; CHECK: vblendvpd
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; CHECK: ret
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define <2 x double> @test8(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vcmpltpd %xmm2, %xmm0, %xmm2
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; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: retq
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%mask = fcmp olt <2 x double> %a, zeroinitializer
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%c = select <2 x i1>%mask, <2 x double>%a, <2 x double>%b
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ret <2 x double>%c
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}
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; CHECK-LABEL: test9
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; CHECK: vpcmpeqd
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; CHECK: vpblendmd
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; CHECK: ret
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define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
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; CHECK-LABEL: test9:
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; CHECK: ## BB#0:
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; CHECK-NEXT: ## kill: YMM1<def> YMM1<kill> ZMM1<def>
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; CHECK-NEXT: ## kill: YMM0<def> YMM0<kill> ZMM0<def>
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; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k1
|
||||
; CHECK-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
|
||||
; CHECK-NEXT: ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
|
||||
; CHECK-NEXT: retq
|
||||
%mask = icmp eq <8 x i32> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
|
||||
ret <8 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test10
|
||||
; CHECK: vcmpeqps
|
||||
; CHECK: vblendmps
|
||||
; CHECK: ret
|
||||
define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: ## kill: YMM1<def> YMM1<kill> ZMM1<def>
|
||||
; CHECK-NEXT: ## kill: YMM0<def> YMM0<kill> ZMM0<def>
|
||||
; CHECK-NEXT: vcmpeqps %zmm1, %zmm0, %k1
|
||||
; CHECK-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
|
||||
; CHECK-NEXT: ## kill: YMM0<def> YMM0<kill> ZMM0<kill>
|
||||
; CHECK-NEXT: retq
|
||||
%mask = fcmp oeq <8 x float> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
|
||||
ret <8 x float> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test11_unsigned
|
||||
; CHECK: vpmaxud
|
||||
; CHECK: ret
|
||||
define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
|
||||
; CHECK-LABEL: test11_unsigned:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask = icmp ugt <8 x i32> %x, %y
|
||||
%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
|
||||
ret <8 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test12
|
||||
; CHECK: vpcmpeqq %zmm2, %zmm0, [[LO:%k[0-7]]]
|
||||
; CHECK: vpcmpeqq %zmm3, %zmm1, [[HI:%k[0-7]]]
|
||||
; CHECK: kunpckbw [[LO]], [[HI]], {{%k[0-7]}}
|
||||
|
||||
define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind {
|
||||
; CHECK-LABEL: test12:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpeqq %zmm2, %zmm0, %k0
|
||||
; CHECK-NEXT: vpcmpeqq %zmm3, %zmm1, %k1
|
||||
; CHECK-NEXT: kunpckbw %k0, %k1, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
; CHECK-NEXT: ## kill: AX<def> AX<kill> EAX<kill>
|
||||
; CHECK-NEXT: retq
|
||||
%res = icmp eq <16 x i64> %a, %b
|
||||
%res1 = bitcast <16 x i1> %res to i16
|
||||
ret i16 %res1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test13
|
||||
; CHECK: vcmpeqps %zmm
|
||||
; CHECK: vpbroadcastd
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test13(<16 x float>%a, <16 x float>%b)
|
||||
; CHECK-LABEL: test13:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcmpeqps %zmm1, %zmm0, %k1
|
||||
; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%cmpvector_i = fcmp oeq <16 x float> %a, %b
|
||||
%conv = zext <16 x i1> %cmpvector_i to <16 x i32>
|
||||
ret <16 x i32> %conv
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test14
|
||||
; CHECK: vpcmp
|
||||
; CHECK-NOT: vpcmp
|
||||
; CHECK: vmovdqu32 {{.*}}{%k1} {z}
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
|
||||
; CHECK-LABEL: test14:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpsubd %zmm1, %zmm0, %zmm1
|
||||
; CHECK-NEXT: vpcmpgtd %zmm0, %zmm1, %k0
|
||||
; CHECK-NEXT: knotw %k0, %k0
|
||||
; CHECK-NEXT: knotw %k0, %k1
|
||||
; CHECK-NEXT: vmovdqu32 %zmm1, %zmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
%sub_r = sub <16 x i32> %a, %b
|
||||
%cmp.i2.i = icmp sgt <16 x i32> %sub_r, %a
|
||||
%sext.i3.i = sext <16 x i1> %cmp.i2.i to <16 x i32>
|
||||
@ -148,12 +179,15 @@ define <16 x i32> @test14(<16 x i32>%a, <16 x i32>%b) {
|
||||
ret <16 x i32>%res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test15
|
||||
; CHECK: vpcmpgtq
|
||||
; CHECK-NOT: vpcmp
|
||||
; CHECK: vmovdqu64 {{.*}}{%k1} {z}
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
|
||||
; CHECK-LABEL: test15:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm1
|
||||
; CHECK-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
|
||||
; CHECK-NEXT: knotw %k0, %k0
|
||||
; CHECK-NEXT: knotw %k0, %k1
|
||||
; CHECK-NEXT: vmovdqu64 %zmm1, %zmm0 {%k1} {z}
|
||||
; CHECK-NEXT: retq
|
||||
%sub_r = sub <8 x i64> %a, %b
|
||||
%cmp.i2.i = icmp sgt <8 x i64> %sub_r, %a
|
||||
%sext.i3.i = sext <8 x i1> %cmp.i2.i to <8 x i64>
|
||||
@ -162,54 +196,65 @@ define <8 x i64> @test15(<8 x i64>%a, <8 x i64>%b) {
|
||||
ret <8 x i64>%res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test16
|
||||
; CHECK: vpcmpled
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test16(<16 x i32> %x, <16 x i32> %y) nounwind {
|
||||
; CHECK-LABEL: test16:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpled %zmm0, %zmm1, %k1
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask = icmp sge <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test17
|
||||
; CHECK: vpcmpgtd (%rdi)
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test17(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
|
||||
; CHECK-LABEL: test17:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpgtd (%rdi), %zmm0, %k1
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%y = load <16 x i32>* %y.ptr, align 4
|
||||
%mask = icmp sgt <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test18
|
||||
; CHECK: vpcmpled (%rdi)
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test18(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
|
||||
; CHECK-LABEL: test18:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpled (%rdi), %zmm0, %k1
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%y = load <16 x i32>* %y.ptr, align 4
|
||||
%mask = icmp sle <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test19
|
||||
; CHECK: vpcmpleud (%rdi)
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test19(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %y.ptr) nounwind {
|
||||
; CHECK-LABEL: test19:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpleud (%rdi), %zmm0, %k1
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%y = load <16 x i32>* %y.ptr, align 4
|
||||
%mask = icmp ule <16 x i32> %x, %y
|
||||
%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test20
|
||||
; CHECK: vpcmpeqd %zmm{{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test20(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i32> %y1) nounwind {
|
||||
; CHECK-LABEL: test20:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k1
|
||||
; CHECK-NEXT: vpcmpeqd %zmm3, %zmm2, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp eq <16 x i32> %x1, %y1
|
||||
%mask0 = icmp eq <16 x i32> %x, %y
|
||||
%mask = select <16 x i1> %mask0, <16 x i1> %mask1, <16 x i1> zeroinitializer
|
||||
@ -217,11 +262,14 @@ define <16 x i32> @test20(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i3
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test21
|
||||
; CHECK: vpcmpleq %zmm{{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa64
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test21(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y1) nounwind {
|
||||
; CHECK-LABEL: test21:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpleq %zmm1, %zmm0, %k1
|
||||
; CHECK-NEXT: vpcmpleq %zmm2, %zmm3, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm2 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm2, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp sge <8 x i64> %x1, %y1
|
||||
%mask0 = icmp sle <8 x i64> %x, %y
|
||||
%mask = select <8 x i1> %mask0, <8 x i1> %mask1, <8 x i1> zeroinitializer
|
||||
@ -229,11 +277,14 @@ define <8 x i64> @test21(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test22
|
||||
; CHECK: vpcmpgtq (%rdi){{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa64
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test22(<8 x i64> %x, <8 x i64>* %y.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
|
||||
; CHECK-LABEL: test22:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpgtq %zmm2, %zmm1, %k1
|
||||
; CHECK-NEXT: vpcmpgtq (%rdi), %zmm0, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp sgt <8 x i64> %x1, %y1
|
||||
%y = load <8 x i64>* %y.ptr, align 4
|
||||
%mask0 = icmp sgt <8 x i64> %x, %y
|
||||
@ -242,11 +293,14 @@ define <8 x i64> @test22(<8 x i64> %x, <8 x i64>* %y.ptr, <8 x i64> %x1, <8 x i6
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @test23
|
||||
; CHECK: vpcmpleud (%rdi){{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
|
||||
; CHECK-LABEL: test23:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpled %zmm1, %zmm2, %k1
|
||||
; CHECK-NEXT: vpcmpleud (%rdi), %zmm0, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp sge <16 x i32> %x1, %y1
|
||||
%y = load <16 x i32>* %y.ptr, align 4
|
||||
%mask0 = icmp ule <16 x i32> %x, %y
|
||||
@ -255,11 +309,13 @@ define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test24
|
||||
; CHECK: vpcmpeqq (%rdi){1to8}
|
||||
; CHECK: vmovdqa64
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
|
||||
; CHECK-LABEL: test24:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k1
|
||||
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%yb = load i64* %yb.ptr, align 4
|
||||
%y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
|
||||
%y = shufflevector <8 x i64> %y.0, <8 x i64> undef, <8 x i32> zeroinitializer
|
||||
@ -268,11 +324,13 @@ define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test25
|
||||
; CHECK: vpcmpled (%rdi){1to16}
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind {
|
||||
; CHECK-LABEL: test25:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpled (%rdi){1to16}, %zmm0, %k1
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%yb = load i32* %yb.ptr, align 4
|
||||
%y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
|
||||
%y = shufflevector <16 x i32> %y.0, <16 x i32> undef, <16 x i32> zeroinitializer
|
||||
@ -281,11 +339,14 @@ define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test26
|
||||
; CHECK: vpcmpgtd (%rdi){1to16}{{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa32
|
||||
; CHECK: ret
|
||||
define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
|
||||
; CHECK-LABEL: test26:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpled %zmm1, %zmm2, %k1
|
||||
; CHECK-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp sge <16 x i32> %x1, %y1
|
||||
%yb = load i32* %yb.ptr, align 4
|
||||
%y.0 = insertelement <16 x i32> undef, i32 %yb, i32 0
|
||||
@ -296,11 +357,14 @@ define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32
|
||||
ret <16 x i32> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test27
|
||||
; CHECK: vpcmpleq (%rdi){1to8}{{.*{%k[1-7]}}}
|
||||
; CHECK: vmovdqa64
|
||||
; CHECK: ret
|
||||
define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
|
||||
; CHECK-LABEL: test27:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vpcmpleq %zmm1, %zmm2, %k1
|
||||
; CHECK-NEXT: vpcmpleq (%rdi){1to8}, %zmm0, %k1 {%k1}
|
||||
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vmovaps %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%mask1 = icmp sge <8 x i64> %x1, %y1
|
||||
%yb = load i64* %yb.ptr, align 4
|
||||
%y.0 = insertelement <8 x i64> undef, i64 %yb, i32 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user